tangxifan
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5da8f1db73
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[Engine] Upgrading fabric generator to connect nets between top module and BL/WL shift register modules
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2021-09-28 23:27:47 -07:00 |
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tangxifan
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7723e00e6c
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[Engine] Adding the function that builds a shift register module for BL/WLs
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2021-09-28 22:49:24 -07:00 |
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tangxifan
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834bdd2b07
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[Engine] Updating fabric generator to support BL/WL shift registers. Still WIP
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2021-09-28 17:29:03 -07:00 |
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tangxifan
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0d72e115ac
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[Engine] Bug fix for the undriven WLR nets in top-level modules
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2021-09-28 11:53:38 -07:00 |
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tangxifan
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e06ac11630
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[Engine] Bug fix
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2021-09-25 19:21:16 -07:00 |
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tangxifan
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74ffc8578f
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[Engine] Upgraded fabric generator to support flatten BL/WL bus for memory banks
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2021-09-24 15:05:25 -07:00 |
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tangxifan
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be4c850d2d
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[Engine] Split the function to add BL/WL configuration bus connections for support flatten BL/WLs
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2021-09-24 12:03:35 -07:00 |
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tangxifan
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18257b3fa1
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[Engine] Update BL/WL port addition for the top-level module in fabric generator
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2021-09-24 11:07:58 -07:00 |
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tangxifan
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7e27c0caf3
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[Engine] Upgrading top-module fabric generation to support QL memory bank with flatten BL/WLs
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2021-09-23 16:16:39 -07:00 |
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tangxifan
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36a4da863c
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[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
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2021-09-20 16:05:36 -07:00 |
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tangxifan
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26b1e48723
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[Engine] Merge BL/WLs in the Grid/CB/SB modules
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2021-09-15 11:27:55 -07:00 |
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tangxifan
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4af6413c97
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[Engine] Fixed a critical bug on WL arrangement; Previously we always consider squart of a local tile. Now we apply global optimization where the number of WLs are determined by the max. number of BLs per column
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2021-09-10 17:03:44 -07:00 |
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tangxifan
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ba1e277dc9
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[Engine] Fix a few bugs in the BL/WL arrangement and now bitstream generator is working fine
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2021-09-10 15:05:46 -07:00 |
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tangxifan
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35c7b09888
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[Engine] Bug fix for mistakes in calculating number of BLs/WLs for QL memory bank
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2021-09-09 15:23:29 -07:00 |
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tangxifan
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1085e468e2
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[Engine] Move most utilized functions for memory bank configuration protocol to a separated source file
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2021-09-05 20:45:56 -07:00 |
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tangxifan
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475ce2c6d9
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[Engine] Upgrade fabric generator in support QL memory bank connections
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2021-09-05 17:49:01 -07:00 |
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tangxifan
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ed80d6b3f4
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[Engine] Place QL memory bank source codes in a separated source file so that integration to OpenFPGA open-source version is easier
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2021-09-05 13:23:38 -07:00 |