tangxifan
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59edd49862
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refactored CMOS MUX buffering
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2019-09-06 16:39:34 -06:00 |
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tangxifan
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bc9d95408e
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bug fixed and refactored intermediate buffer addition
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2019-09-05 16:09:28 -06:00 |
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tangxifan
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e623c19055
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implementing mux Verilog generation. Bugs detected, fixing ongoing
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2019-09-04 23:54:53 -06:00 |
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tangxifan
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fde9c8b4ec
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add frac_lut outputs to mux_graph generation
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2019-09-03 23:19:24 -06:00 |
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tangxifan
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b6bb433edc
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bug fixing for datapath mux size in Verilog generation
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2019-09-03 18:09:21 -06:00 |
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tangxifan
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4d183a3fe4
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start developing mux Verilog module generation
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2019-09-03 16:59:03 -06:00 |
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tangxifan
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d2d750a15c
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debugged rram mux branch Verilog generation
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2019-09-02 16:21:29 -06:00 |
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tangxifan
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395bf4fbdf
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refactored rram mux generation
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2019-09-02 14:30:18 -06:00 |
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tangxifan
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f04565386f
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refactored behavioral mux branch verilog generation
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2019-08-27 18:39:25 -06:00 |
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tangxifan
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ab6f1a5461
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add mux output ids for mux_graph
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2019-08-26 21:21:50 -06:00 |
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tangxifan
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c43fabb43c
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developed verilog instance writer. refactoring on mux ongoing
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2019-08-25 10:31:45 -06:00 |
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tangxifan
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fe7dfd59c3
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Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
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2019-08-24 23:54:37 -06:00 |
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tangxifan
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63f40f48fa
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develop and plug mux_lib_builder, refactoring the mux submodule generation
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2019-08-24 19:23:33 -06:00 |
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tangxifan
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39853408dd
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add recursive global port searching for circuit library
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2019-08-23 20:23:41 -06:00 |
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tangxifan
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37a092e885
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add recursive global port searching for circuit library
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2019-08-23 16:36:30 -06:00 |
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tangxifan
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7b0c55ce15
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try to reduce precision in timing assignment of Verilog netlist (travis iverilog was not happy)
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2019-08-21 22:45:48 -06:00 |
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tangxifan
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9c43b1b753
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complete refacotriing the inv and buf part in submodules
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2019-08-21 14:54:05 -06:00 |
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tangxifan
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a40e5c91ca
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refactored power-gate inverter
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2019-08-20 21:56:55 -06:00 |
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tangxifan
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19472ace4e
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renaming files
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2019-08-20 21:01:38 -06:00 |