tangxifan
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bcb82d43af
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[core] code format
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2023-09-06 22:40:59 -07:00 |
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tangxifan
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2fee56548b
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[core] fixed some bugs
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2023-09-06 22:39:59 -07:00 |
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tangxifan
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f544953085
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[core] code format
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2023-09-06 22:29:30 -07:00 |
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tangxifan
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f8b2eec988
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[core] now default net type wire will not appear. timescale does not show in fabric netlists
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2023-09-06 22:27:51 -07:00 |
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tangxifan
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539bcba851
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[core] now default nettype is reverted to 'wire' at the end of each module; Being compatible with Verilog 2001 standard; Avoid unnecessary impacts on netlists which do not explicitly define default net types
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2023-09-06 17:23:41 -07:00 |
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tangxifan
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6d31b319a2
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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tangxifan
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671188dfa4
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[FPGA-Verilog] Now support big/little-endian in bus group
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2022-02-18 23:05:03 -08:00 |
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tangxifan
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62b57b05d2
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[Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp``
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2022-01-25 12:09:08 -08:00 |
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tangxifan
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a56d1f4fdb
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[FPGA-Verilog] Upgraded testbench generator to support memory bank using flatten BL/WLs
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2021-09-25 17:49:15 -07:00 |
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tangxifan
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b787c4e100
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[Engine] Register QL memory bank as a legal protocol
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2021-09-09 15:06:51 -07:00 |
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tangxifan
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ae6a46cd60
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[Tool] Add a new command write_full_testbench which outputs self-testable full testbench which loads external bitstream file; Currently only support configuration chain without fast configuration technique
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2021-06-03 15:41:11 -06:00 |
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tangxifan
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fa11410425
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[Tool] Remove exceptions on outputing verilog port with lsb=0
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2021-03-17 20:27:08 -06:00 |
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tangxifan
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73461971d2
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[Tool] Bug fix for printing single-bit ports in Verilog netlists
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2021-02-28 16:12:57 -07:00 |
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tangxifan
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15e26a5602
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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tangxifan
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1b4e449179
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[OpenFPGA Tool] Critical bug fix for Verilog testbenches for memory bank and frame-based configuration protocol
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2020-09-25 21:05:20 -06:00 |
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tangxifan
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e9937954f2
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optimizing the constant writing in Verilog for single bits
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2020-06-29 12:29:25 -06:00 |
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tangxifan
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3c10af7f2b
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bug fixed in memory bank configuration protocol which is due to the wrong Verilog port merging algorithm
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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8ec8ac4118
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bug fixed in flatten memory organization. Passed verification
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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5f4e7dc5d4
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support gpinput and gpoutput ports in module manager and circuit library
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2020-04-05 16:52:21 -06:00 |
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tangxifan
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836f722f20
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start supporting global output ports in module manager
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2020-04-05 15:19:46 -06:00 |
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tangxifan
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11775c370b
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bring FPGA top module verilog writer online. Fabric Verilog generator done
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2020-02-16 16:18:14 -07:00 |
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tangxifan
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c6c3ef71f3
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adapt all the Verilog submodule writers and bring it onlien
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2020-02-16 13:35:18 -07:00 |
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tangxifan
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2eba882332
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put verilog submodules online. ready to bring the how submodule writer online
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2020-02-16 11:41:20 -07:00 |
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tangxifan
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0d5292ad0d
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adapt verilog writer utils
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2020-02-15 23:26:59 -07:00 |