tangxifan
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36a4da863c
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[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
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2021-09-20 16:05:36 -07:00 |
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tangxifan
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fed975c52a
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[Tool] Add postfix removal support in write_io_mapping command
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2021-06-18 16:13:50 -06:00 |
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tangxifan
|
73461971d2
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[Tool] Bug fix for printing single-bit ports in Verilog netlists
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2021-02-28 16:12:57 -07:00 |
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tangxifan
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4cc8b08a6c
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[Tool] Add openfpga version display
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2021-01-23 16:38:00 -07:00 |
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tangxifan
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cc91a0aebd
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[Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder
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2021-01-04 17:14:26 -07:00 |
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tangxifan
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b78f8bec16
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[Tool] Bug fixed for multi-region configuration frame
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2020-10-30 21:19:20 -06:00 |
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tangxifan
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fc6bfdc7a2
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[OpenFPGA Code] Patch syntax compatibility for older gcc
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2020-09-14 18:55:21 -06:00 |
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tangxifan
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2712c354a9
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now physical pb_port binding support multiple ports
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2020-08-18 12:38:56 -06:00 |
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tangxifan
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1ad6e8292a
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move constants from verilog domain to common so that FPGA-SPICE can share
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2020-07-05 11:39:46 -06:00 |
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tangxifan
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2a9377b3f4
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use encoded address in storage of fabric bitstream to save memory
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2020-07-03 15:12:29 -06:00 |
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tangxifan
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9f19c36a89
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use char in fabric bitstream to save memory footprint
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2020-07-02 15:56:50 -06:00 |
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tangxifan
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b36da17a08
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bug fix for directory creation when the input is an empty string
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2020-06-25 10:34:34 -06:00 |
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tangxifan
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675a59ecb8
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Move fpga_bitstream to the libopenfpga library and add XML reader
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2020-06-20 18:25:17 -06:00 |
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tangxifan
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b8c449d520
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add comments for decoding functions to help debugging the frame-based decoders
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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6aff33dd35
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add fabric hierarchy writer
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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8726c618eb
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add time unit support on SDC generator. Now users can define time_unit thru cmd-line options
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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8695c5ee78
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add options to use general-purpose wildcards in SDC generator
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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1fb37f4c71
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improve directory creator to support same functionality as 'mkdir -p'
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2020-04-08 12:55:09 -06:00 |
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tangxifan
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c6c3ef71f3
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adapt all the Verilog submodule writers and bring it onlien
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2020-02-16 13:35:18 -07:00 |
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tangxifan
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a88c4bc954
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add decode utils to libopenfpga and adapt local decoder writer in Verilog
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2020-02-16 12:21:59 -07:00 |
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tangxifan
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622c7826d1
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start transplanting fpga_verilog
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2020-02-15 15:03:00 -07:00 |
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tangxifan
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99f5a86b49
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bug fixed for routing annotation and routing net fix-up
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2020-02-06 12:54:55 -07:00 |
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tangxifan
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7d4b07421d
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finish XML parser and writer for pb_type annotation
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2020-01-26 15:54:49 -07:00 |
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tangxifan
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1cba141dd0
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add pb parser and support XML parsing for pb type name in full hiearchy
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2020-01-26 11:52:58 -07:00 |
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tangxifan
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3ace7f8ef7
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move generic data structures to openfpgautil library
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2020-01-16 13:26:55 -07:00 |
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tangxifan
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d232391250
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developed XML writer for circuit library and start porting functions to openfpgautil library
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2020-01-16 12:32:29 -07:00 |