Commit Graph

3317 Commits

Author SHA1 Message Date
tangxifan af21aa0522 [Test]Try env variable for parallel cmake build 2020-11-23 20:52:07 -07:00
tangxifan 7bd2622fd6 [Test] Try parallel build for Cmake in github actions 2020-11-23 20:50:19 -07:00
tangxifan 84c39315a5 [Test] Use example CMake build scripts from Github actions 2020-11-23 20:40:05 -07:00
tangxifan de44e8c9d1 [Test] Bug fix for github actions 2020-11-23 20:24:18 -07:00
tangxifan a95ddef90d [Test] Bug fix in calling scripts for Github Actions 2020-11-23 20:22:59 -07:00
tangxifan f2b6655550 [Test] Start porting to Github Actions with build test 2020-11-23 20:19:44 -07:00
tangxifan c82f01b3ab [Tool] Use conditional operator in signal initialization to eliminate all the warning messages 2020-11-23 15:50:23 -07:00
tangxifan b857135f4e [Doc] Add clarification about which cells are applicable for signal initialization 2020-11-23 15:19:15 -07:00
tangxifan 2b9a97729e [Doc] Update documentation to clarify the port sequence for MUX2 and pass-gate logic circuit models 2020-11-23 15:09:47 -07:00
tangxifan e644545f21 [Doc] Remove signal initialization for select ports of MUXes and Pass-gates; Use urandom to generate just-fit random vectors 2020-11-23 15:02:06 -07:00
tangxifan 6ba02f35ca
Merge pull request #130 from antmicro/rr_graph_load_fix
Fix for rr graph loading by VPR
2020-11-23 09:31:29 -07:00
Maciej Kurc 3d38e76c8f Disabled printing segment ids for non-channel nodes.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2020-11-23 17:07:28 +01:00
Maciej Kurc b6728cf2d9 Added loading rr node segment indices
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2020-11-23 14:53:50 +01:00
Laboratory for Nano Integrated Systems (LNIS) b78803a6bb
Merge pull request #129 from LNIS-Projects/dev
Generate Signal Initialization in Verilog Testbenches rather than HDL netlists
2020-11-22 21:48:22 -07:00
tangxifan fd80cacaa3 [Flow] Add example script for behaviorial verilog generation 2020-11-22 21:14:10 -07:00
tangxifan 617f7e3062 [Flow] disable signal initialization for behavioral verilog generation 2020-11-22 21:13:22 -07:00
tangxifan 5eb04e6fff [HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals 2020-11-22 20:53:32 -07:00
tangxifan fd0e6814ea [Doc] Update documentation about the pre-processing flags 2020-11-22 20:33:15 -07:00
tangxifan 3b2a4c5387 [Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists 2020-11-22 20:25:03 -07:00
tangxifan 655da9f3d0 [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
tangxifan 348872f8a4 [Flow] Adapt OpenFPGA shell script for the preprocessing flag option changes 2020-11-22 16:12:28 -07:00
tangxifan 57a24570f5 [Tool] Move icarus and signal initialization options to testbench generator 2020-11-22 16:01:31 -07:00
Laboratory for Nano Integrated Systems (LNIS) a00752938b
Merge pull request #127 from LNIS-Projects/dev
Bug fix for global clock port using physical tile pins
2020-11-17 15:56:08 -07:00
tangxifan 845436fa71 [Test] Add sequential benchmark for global tile clock test case 2020-11-17 14:34:54 -07:00
tangxifan 91b0dbbaa2 [Script] Add example openfpga shell run script when using global tile clocks 2020-11-17 14:33:12 -07:00
Laboratory for Nano Integrated Systems (LNIS) 3a80af3408
Merge pull request #126 from LNIS-Projects/dev
Multiple Bug Fixes
2020-11-13 16:44:58 -07:00
tangxifan 3f91b8433e [Tool] Change the i/o numbering to the clockwise sequence 2020-11-13 15:00:25 -07:00
tangxifan 088198c861 [Tool] enhance error checking in fabric key parser 2020-11-13 10:56:00 -07:00
Laboratory for Nano Integrated Systems (LNIS) c05de43927
Merge pull request #124 from LNIS-Projects/dev
Add readthedoc Setting File
2020-11-12 21:12:05 -07:00
tangxifan cb025e982f [Doc] Add readthedoc setting file 2020-11-12 19:43:43 -07:00
Laboratory for Nano Integrated Systems (LNIS) 32da241edd
Merge pull request #123 from LNIS-Projects/dev
Add Illustrative Example to Documentation to Explain the Difference on Global Port Definitions between Circuit Model and Tile Annotation
2020-11-12 10:23:33 -07:00
tangxifan f6126d1ed6 [Doc] Add illustrative example to diff between global ports definitions 2020-11-12 09:24:39 -07:00
Laboratory for Nano Integrated Systems (LNIS) 2af49c245f
Merge pull request #122 from LNIS-Projects/dev
Support Global Port Definition for Physical Tile Ports
2020-11-11 16:16:32 -07:00
tangxifan 372fb261fd [Tool] Extend the support on global tile port for I/O tiles 2020-11-11 15:09:40 -07:00
tangxifan bc43c876b0 [Doc] Update documentation for the rules in global port definition for tile ports 2020-11-11 14:10:11 -07:00
tangxifan e959821813 [Tool] Enhance internal check functions for tile annotation 2020-11-11 13:59:24 -07:00
tangxifan e627b6dd5d [Tool] Enhance port attribute checks in tile annotation data structure 2020-11-11 13:41:05 -07:00
tangxifan 9cbc374b33 [Tool] Add check codes for tile annotation 2020-11-11 12:03:13 -07:00
tangxifan 81e56d45d6 [Tool] Update FPGA-SDC to use the new data structure for global ports 2020-11-10 21:17:17 -07:00
tangxifan 2c269c532a [Doc] Update doc for the global port definition using physical tile port 2020-11-10 20:48:28 -07:00
tangxifan 4dc0fb81c5 [Tool] Bug fix for clang compilation error 2020-11-10 20:32:58 -07:00
tangxifan c61ec5a8b8 [Tool] Bug fix for defining global ports from tiles 2020-11-10 20:31:14 -07:00
tangxifan 05f5ce38ea [Test] Deploy new test to CI 2020-11-10 20:31:03 -07:00
tangxifan 485258a9ea [Test] Add test case for global clock from tiles 2020-11-10 19:24:25 -07:00
tangxifan f29916921a [Arch] Add openfpga arch for using global clocks from tiles 2020-11-10 19:20:08 -07:00
tangxifan a6531d9e8d [Arch] Add k4 arch using global clock from tile port (with zero fc) 2020-11-10 19:17:34 -07:00
tangxifan dcb50e4f19 [Tool] Use use standard data structure to store global port information 2020-11-10 19:07:28 -07:00
tangxifan cbb1545ee3 [Tool] Add connection builder for tile global ports to top-level module 2020-11-10 16:59:00 -07:00
tangxifan 67af145455 [Tool] Add XML writer for tile annotation 2020-11-10 14:51:46 -07:00
tangxifan 75ce4b5e25 [Arch] Fine tune example arch 2020-11-10 14:38:47 -07:00