tangxifan
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123bb70cb3
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[Doc] More explanantion on the use of config_enable attribute for circuit ports
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2022-02-23 15:53:58 -08:00 |
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tangxifan
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57159fc121
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[Doc] Update documentation for the new syntax in configuration protocol and fabric key file format
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2021-10-10 17:46:45 -07:00 |
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tangxifan
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40b589dc6d
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[Doc] Update documentation about the clock definition for programming clocks in simulation settings
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2021-10-06 13:50:33 -07:00 |
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tangxifan
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ff339312f6
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[Doc] Update documentation about the limitations of multi-region configuration protocols
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2021-10-05 11:55:10 -07:00 |
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tangxifan
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a01fa7c282
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[Doc] Add figures and text to explain the difference between the XML syntax for QuickLogic memory bank
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2021-10-04 12:09:42 -07:00 |
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tangxifan
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b0a97a7052
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[Doc] Update doc about WLR usage for QL memory bank
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2021-09-27 10:24:04 -07:00 |
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tangxifan
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f9bceff33a
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[Doc] Update documentation for the flatten BL/WL protocols
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2021-09-25 20:44:45 -07:00 |
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tangxifan
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d9d959709c
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[Doc] Add missing figures
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2021-09-20 20:31:53 -07:00 |
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tangxifan
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3146d2484f
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[Doc] Update documentation on the WLR definition for circuit model
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2021-09-20 17:21:33 -07:00 |
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tangxifan
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73d21c9730
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[Doc] Update doc about how to use the QuickLogic memory bank
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2021-09-10 15:30:37 -07:00 |
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tangxifan
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9b40e74e25
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[Doc] Add example circuit models for multipliers and update technical highlight with links to the examples
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2021-05-24 15:24:50 -06:00 |
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tangxifan
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21a18069a1
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[Doc] Add example circuit about dual-port RAMs to documentation; Updated technical highlights by providing links to the examples
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2021-05-24 14:50:55 -06:00 |
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tangxifan
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b6b98a75b8
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[Doc] Add example circuit model about multi-mode flip-flops; Separate data-path FF circuit model and configuration-chain FF circuit model;
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2021-05-24 13:03:40 -06:00 |
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tangxifan
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62dc5a3856
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[Doc] Update documentation about the new syntax introduced for pin binding between operating modes and physical modes
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2021-04-24 16:02:24 -06:00 |
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tangxifan
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19b2641839
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Merge branch 'master' into doc_patch
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2021-03-15 11:45:32 -06:00 |
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tangxifan
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fb7d76545e
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[Doc] Patch the schematic of LUT circuit models to be consistent with netlists
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2021-03-15 11:40:09 -06:00 |
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tangxifan
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ff0faeb285
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[Doc] Update documentation about the extended bitstream setting
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2021-03-10 21:41:59 -07:00 |
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tangxifan
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01b9bf2a02
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[Doc] Update num_region XML for config protocol
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2021-02-18 21:58:30 -07:00 |
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tangxifan
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1c4dc9f74b
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[Doc] Update documentation about the super LUT feature
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2021-02-10 11:49:59 -07:00 |
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tangxifan
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9c5368f912
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[Doc] Correct bugs in compiling latexpdf
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2021-02-07 16:17:54 -07:00 |
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tangxifan
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9b5c64f35f
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[Doc] Update documentation about disable_packing syntax
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2021-02-04 16:41:24 -07:00 |
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tangxifan
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d53d3963d4
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[Doc] Broken link fix in config protocol documentation
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2021-01-26 14:05:11 -07:00 |
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tangxifan
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e9dc708d66
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[Doc] Group file format documentation into a unified section
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2021-01-19 19:44:44 -07:00 |
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tangxifan
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c4d3e7c50c
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[Doc] Update documentation for the new XML syntax in simulation settings
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2021-01-15 12:30:26 -07:00 |
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tangxifan
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0c808bec41
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[Doc] Add clarification for defining multi-bit global tile ports
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2021-01-09 20:00:16 -07:00 |
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tangxifan
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2324edc522
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[Doc] Update documentation for upgraded tile annotation
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2021-01-09 18:55:16 -07:00 |
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tangxifan
|
226f6b8d6d
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[Doc] Update documentation about FF circuit models to show capability in modeling SCFFs
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2021-01-04 18:30:04 -07:00 |
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tangxifan
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406edeec89
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[Doc] Typo fix
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2020-12-04 15:07:02 -07:00 |
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tangxifan
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4fe190fa7e
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[Doc] Bug fix in LUT circuit model documentation
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2020-12-04 14:44:27 -07:00 |
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tangxifan
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8350b0f911
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[Doc] Update documentation about default value definition in tile annotation
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2020-12-02 17:08:34 -07:00 |
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tangxifan
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cc0114459a
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[Doc] Enrich examples for LUT circuit models
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2020-11-26 13:03:12 -07:00 |
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tangxifan
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62e804215b
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[Doc] Add svg figures for LUT examples
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2020-11-26 12:35:39 -07:00 |
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tangxifan
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2b9a97729e
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[Doc] Update documentation to clarify the port sequence for MUX2 and pass-gate logic circuit models
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2020-11-23 15:09:47 -07:00 |
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tangxifan
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f6126d1ed6
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[Doc] Add illustrative example to diff between global ports definitions
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2020-11-12 09:24:39 -07:00 |
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tangxifan
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bc43c876b0
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[Doc] Update documentation for the rules in global port definition for tile ports
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2020-11-11 14:10:11 -07:00 |
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tangxifan
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2c269c532a
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[Doc] Update doc for the global port definition using physical tile port
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2020-11-10 20:48:28 -07:00 |
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tangxifan
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056b7c0c79
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[Doc] Update documentation about CCFF circuit model examples
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2020-11-06 12:22:22 -07:00 |
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tangxifan
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849ecc7fc0
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[Doc] Add notes for using the is_data_io syntax
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2020-11-05 09:30:19 -07:00 |
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tangxifan
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9bce2f3818
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[Doc] Update documentation for new XML syntax "is_data_io"
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2020-11-05 09:28:46 -07:00 |
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tangxifan
|
7e940980e1
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[Doc] Update documentation about configuration regions for frame-based protocol
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2020-10-30 21:52:01 -06:00 |
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tangxifan
|
c2c384e24b
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[Doc] update documentation about memory bank definition
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2020-10-29 17:04:25 -06:00 |
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tangxifan
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ccaa697e5a
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[Documentation] Add links to technical features to examples
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2020-10-10 22:40:37 -06:00 |
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tangxifan
|
639d57016b
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[Documentation] Update documentation about the multi-region configuration
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2020-09-29 15:55:42 -06:00 |
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tangxifan
|
462886fb5f
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[Documentation] Update documentation for the multiple region support on configuration chain
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2020-09-29 14:02:03 -06:00 |
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tangxifan
|
7a2502ddf9
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[documentation] add more guidelines about the vpr-openfpga architecture annotation
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2020-09-02 22:47:14 -06:00 |
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tangxifan
|
ac8e937a50
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[Documentation] Update for default circuit model rules
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2020-08-23 14:08:38 -06:00 |
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tangxifan
|
fb5a5a2448
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[documentation] remove the limitation on through channels
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2020-08-19 20:12:49 -06:00 |
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tangxifan
|
47f15729ad
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update doc about the limitation on using tileable routing
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2020-08-19 18:37:28 -06:00 |
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tangxifan
|
d6d17675e2
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update docoumentation about the constraints when using tileable rr_graph generator
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2020-08-19 18:01:32 -06:00 |
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tangxifan
|
161d660837
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update documentation for the initial offset when mapping physical pins
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2020-08-19 15:00:46 -06:00 |