tangxifan
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4b852afeac
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skip rotating mirror detection which is too time-consuming
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2019-05-25 23:41:46 -06:00 |
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tangxifan
|
22e71f5847
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Add rotate one side of switch block functionality
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2019-05-25 22:48:07 -06:00 |
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tangxifan
|
858a323228
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Add more support for rotating Switch Blocks
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2019-05-25 21:26:35 -06:00 |
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tangxifan
|
2eab0b1c1c
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update unique_mirror search algorithm for Switch Blocks
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2019-05-25 19:54:15 -06:00 |
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tangxifan
|
d3eae80e64
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implemented an native way in finding rotable Switch blocks
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2019-05-25 19:37:18 -06:00 |
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tangxifan
|
ae0248fbc6
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debugging SwitchBlock rotating
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2019-05-24 23:10:30 -06:00 |
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tangxifan
|
9adc2945c8
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add rotate functionality for RRSwitchBlock
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2019-05-24 21:40:16 -06:00 |
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tangxifan
|
eef1312325
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updated bitstream to use new RRSwitchBlock as well as the report timing engine
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2019-05-24 12:54:10 -06:00 |
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tangxifan
|
8f4f590ff9
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update Verilog compact_netlist outputter with RRSwitchBlock classes
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2019-05-23 21:52:12 -06:00 |
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tangxifan
|
ea8c36ce6e
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upgrade Verilog SB generator using the RRSwitchBlock
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2019-05-23 17:37:39 -06:00 |
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tangxifan
|
4aab93b729
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update class rr_switch_block and be ready for updating the downstream verilog generator
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2019-05-22 22:04:31 -06:00 |
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tangxifan
|
efbc454cdd
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Add Class for RRSwtichBlock and plug-in to replace the old t_sb
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2019-05-22 12:34:06 -06:00 |
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tangxifan
|
ec3b4c86c4
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update file organization and be ready for SB/CB class
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2019-05-21 12:15:38 -06:00 |
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tangxifan
|
8186d6dd11
|
reorganize files and clean some warnings
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2019-05-21 10:17:54 -06:00 |
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tangxifan
|
b185a17359
|
add routing_channel unique module generation
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2019-05-20 22:33:17 -06:00 |
Baudouin Chauviere
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b48a27acf0
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-13 14:45:57 -06:00 |
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Baudouin Chauviere
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2019840d7c
|
cleaned unused variables
|
2019-05-13 14:45:02 -06:00 |
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tangxifan
|
3313eac23b
|
add rr_chan obj
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2019-05-10 22:50:08 -06:00 |
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tangxifan
|
be4643b8a6
|
updated Verilog generator to use compact CBs and SBs. SPICE generator to be updated
|
2019-05-10 10:21:06 -06:00 |
|
tangxifan
|
5c646f5de7
|
fix bugs in routing identification
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2019-05-09 21:40:06 -06:00 |
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tangxifan
|
a9df922412
|
finish the identification on mirror switch and connection blocks
Verilog generator to be updated
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2019-05-09 21:31:39 -06:00 |
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tangxifan
|
a3c3f2b892
|
developing compact routing hierarchy
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2019-05-08 20:49:21 -06:00 |
|
tangxifan
|
42daadee2f
|
critical bug fixing
|
2019-04-30 14:30:17 -06:00 |
|
tangxifan
|
46d44fa42a
|
Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |