tangxifan
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1b13e8ecb1
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[Architecture] Bug fix in the SRAM Verilog
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2020-09-24 12:26:13 -06:00 |
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tangxifan
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83971bba41
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[Architecture] Update cell ports for native SRAM cell
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2020-09-24 10:31:31 -06:00 |
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tangxifan
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6bb30ab33c
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[Architecture] Enrich SRAM Verilog HDL for flexible set/reset support
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2020-09-24 10:02:51 -06:00 |
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tangxifan
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fcf1ff418f
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[Architecture] Add Verilog for SRAM using set/reset
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2020-09-23 21:53:38 -06:00 |
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tangxifan
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baa2c6b7ef
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update arch to support reset signal for SRAm
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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82b04ae3f0
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add SRAM verilog for memory bank usage
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2020-06-11 19:31:14 -06:00 |
Ganesh Gore
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7bfc48b8e4
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Moved spice and verilog netlist folder location
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2019-08-17 01:49:49 -06:00 |