Commit Graph

122 Commits

Author SHA1 Message Date
tangxifan 36603f9772
Merge branch 'master' into vtr_upgrade 2022-09-20 21:08:06 -07:00
tangxifan e0f632cc9c [test] fixed a bug 2022-09-20 20:29:34 -07:00
tangxifan 645d8df7b9 [test] fixed a bug 2022-09-20 20:09:41 -07:00
tangxifan 9042fc2422 [test] now reg test should show diff details when failed 2022-09-20 19:32:34 -07:00
tangxifan da157ed5de [test] debugging git-diff 2022-09-20 15:31:39 -07:00
tangxifan 6a896a9845 [test] debugging 2022-09-20 14:08:22 -07:00
tangxifan ecfdc4a83a [test] debugging 2022-09-20 13:51:32 -07:00
tangxifan bdcdc7d294 [test] Now git diff in basic regression tests should capture the changes on golden outputs 2022-09-20 13:36:31 -07:00
tangxifan 373566416c Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade 2022-09-16 16:47:21 -07:00
tangxifan a2e22787c2 [test] deploy the new test cases to the basic regression tests 2022-09-16 10:31:15 -07:00
tangxifan 91fe27ff66 [test] deploy new test to ci 2022-09-09 17:00:28 -07:00
tangxifan 95d7a17b3c Merge branch 'master' into vtr_upgrade 2022-09-09 14:32:42 -07:00
tangxifan a840aeea7a [test] add a new test to validate custom I/O location syntax and deploy to basic regression tests 2022-09-08 16:27:11 -07:00
tangxifan 56619f9a47 Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade 2022-09-07 15:04:05 -07:00
tangxifan 93ab992187 [test] update golden outputs without time stamps 2022-09-06 14:59:00 -07:00
tangxifan 9e1abf5898
Merge branch 'master' into vtr_upgrade 2022-09-01 21:39:14 -07:00
tangxifan c48f750f86 [test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit 2022-09-01 20:10:29 -07:00
tangxifan 71ad0721a1
Merge branch 'master' into vtr_upgrade 2022-08-31 13:56:17 -07:00
tangxifan 201bca8968 [test] typo 2022-08-30 08:59:20 -07:00
tangxifan 5f88b9a226 [test] typo 2022-08-29 22:41:15 -07:00
tangxifan 0b5bdcdbb1 [test] deploy new test to basic regression tests 2022-08-29 22:07:56 -07:00
tangxifan 8d6682c28b [test] fixed a bug when removing previous runs 2022-08-25 16:20:18 -07:00
tangxifan 6ce1d4804c [test] deploy new test case to basic regression tests 2022-08-01 21:05:05 -07:00
taoli4rs 347a29f27c Fix test name in basic regression test script. 2022-07-20 21:05:31 -07:00
taoli4rs cfc0d08060 Add constrain_pin_location command in openfpga; add full flow test. 2022-07-20 11:51:00 -07:00
tangxifan 9832722056 [test] now add QuickLogic memory bank to fpga bitstream regression tests 2022-05-25 11:42:32 +08:00
tangxifan 86347a9d49 [test] move generate_bitstream to another directory. Ready to test generate bitstream across different configuration protocols 2022-05-25 11:19:49 +08:00
tangxifan 7d694acf32 [test] debugging basic reg test paths 2022-05-23 11:21:36 +08:00
tangxifan b41cbad5d3 [test] force to run git diff under root directory 2022-05-23 10:32:43 +08:00
tangxifan 488a934097 [test] give abs path for git diff in basic regression tests 2022-05-23 09:12:33 +08:00
tangxifan 0dc7caf3b7 [test] now regression test script supports remove all run dir through command-line options 2022-05-22 13:15:39 +08:00
tangxifan 751d87b8e3 [test] fix a bug in detect changes in golden netlists 2022-05-22 13:06:47 +08:00
tangxifan d7e854eae7 [test] deploy new test to ci 2022-05-09 17:23:57 +08:00
Ganesh Gore 522982c9ba Adde vtr_benchmarks_template for demo 2022-05-06 22:40:36 -06:00
Ganesh Gore 1e243650b9 Added option to copy example projects 2022-05-03 14:06:16 -06:00
Ganesh Gore 21c3dbf611 Added regression for template project 2022-05-02 23:23:45 -06:00
tangxifan 9bd66d531e [Test] Deploy the new test case to basic regression tests 2022-04-13 16:06:27 +08:00
tangxifan 3e3a65223c [Test] Deploy new test case to basic regression tests 2022-03-20 11:04:07 +08:00
tangxifan a615c9d4e3 [Test] Rename test cases 2022-02-24 09:43:41 -08:00
tangxifan b27a04eb24 [Test] Now test case has a config done CCFF 2022-02-23 22:07:11 -08:00
tangxifan cf31879b20 [Test] Deploy new test to basic regression tests 2022-02-23 16:03:56 -08:00
tangxifan 68644ea0f6 [Test] Add the new test to basic regression tests 2022-02-18 15:44:07 -08:00
tangxifan fe9e0ff977 [Test] Add the new test to basic regression tests 2022-02-18 15:38:53 -08:00
tangxifan 85c893c94c [Test] Add new test to basic regression tests 2022-02-18 15:30:08 -08:00
tangxifan 43d852d8a1 [Test] Add the bus group test case to basic regression tests 2022-02-18 12:27:25 -08:00
tangxifan d667102a43 [Test] Add new test case to regression tests 2022-02-14 15:58:53 -08:00
tangxifan 0268814fc6 [Test] Splitting counter benchmarks into 2 categories; One has Verilog-to-Verification tests, while the other has only Verilog-to-Bitstream tests 2022-02-14 12:20:56 -08:00
tangxifan 27ac2fafe5 [Test] Add the new test case to regression tests 2022-02-01 13:45:46 -08:00
tangxifan 9871fe88fb [Test] Typo fix 2022-01-31 13:03:45 -08:00
tangxifan da8fc0f5d4 [Test] Add a new test case to validate ``--use_relative_path`` 2022-01-31 13:02:19 -08:00