Commit Graph

417 Commits

Author SHA1 Message Date
tangxifan a9df922412 finish the identification on mirror switch and connection blocks
Verilog generator to be updated
2019-05-09 21:31:39 -06:00
tangxifan a3c3f2b892 developing compact routing hierarchy 2019-05-08 20:49:21 -06:00
tangxifan 4c6639218e Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-08 14:30:33 -06:00
tangxifan e305e60ee4 minor fix on the shell interface of VPR 2019-05-08 14:29:58 -06:00
Baudouin Chauviere 4f386de2ef gen_xxx functions create mem-leaks because the mem is dynamically allocated inside and not freed. TBD later everywhere 2019-05-06 17:25:29 -06:00
Baudouin Chauviere 3b62f8e024 Conversion from s to ns for the loop breaking delays 2019-05-06 16:12:30 -06:00
Baudouin Chauviere a5a1a376ab Modified code for cleaner delay naming convention 2019-05-06 12:52:49 -06:00
tangxifan 4e3487b691 Add latest abc and update ace dependence 2019-05-03 18:56:03 -06:00
Baudouin Chauviere 7860042276 added before after loop breaker constraining 2019-05-03 14:00:06 -06:00
Baudouin Chauviere 4e330ee463 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-03 10:43:22 -06:00
Baudouin Chauviere 921b694400 Bug fix sdc breaking loop of edges outside current interconnect 2019-05-03 10:42:35 -06:00
AurelienUoU 42f20eda60 Add the user matching for internal register in formal verification script generation 2019-05-03 10:24:02 -06:00
tangxifan 974af5a2ae Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-04-30 14:30:38 -06:00
tangxifan 42daadee2f critical bug fixing 2019-04-30 14:30:17 -06:00
Baudouin Chauviere 1ab4688339 Create no segment constraint in loop_breaker if none is given by user 2019-04-30 12:30:07 -06:00
tangxifan c46c0fc97d bug fixing for SDC generator 2019-04-26 14:07:44 -06:00
tangxifan 46d44fa42a Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00