1c5bede282
update arch file with device technology binding information
2020-07-13 19:06:51 -06:00
73e75bf456
add readme for OpenFPGA architecture naming
2020-07-01 10:27:21 -06:00
60dd37e086
remove simulation settings from openfpga arch XML
...
update travis to split CI tests
fix errors in travis configuration
fixing travis errors in scripts
keep fixing travis
fix travis on build.sh
bug fixing in travis CI
bug fix in travis regression test run
fixing bugs in the travis scripts
bug fix in travis script: remove common.sh in regression test call
keep bug fixing in travis
2020-06-11 19:31:17 -06:00
baa2c6b7ef
update arch to support reset signal for SRAm
2020-06-11 19:31:14 -06:00
aac2e8c805
update openfpga architecture for memory bank usage
2020-06-11 19:31:14 -06:00
a1ec6833c2
add memory bank example arch xml
2020-06-11 19:31:13 -06:00
8b5b221a21
add new architecture for standalone memory organization
2020-06-11 19:31:12 -06:00
6a72c66eb8
bug fixed for frame-based configuration memory in top-level full testbench
2020-06-11 19:31:11 -06:00
3fa3b17061
start testing the frame-based configuration protocol. To distinguish, rename xml to identify between configuration chain and frame-based. This should not impact the pre-config testbenches.
2020-06-11 19:31:10 -06:00
4083fae41a
add new test cases about user-defined simulation settings
2020-06-11 19:31:03 -06:00
2fbf9c2cfc
change to a higher simulation clock speed to accelerate CI verification.
...
Later, we should place simulation information in another XML so that we can reuse that easily
2020-06-11 19:31:03 -06:00
889bc8dbe8
add more test cases about LUT design and deploy to CI
2020-06-11 19:31:02 -06:00
889f179ce7
add local encoder test case
2020-06-11 19:31:01 -06:00
73e9006372
add arch file with spy pads
2020-04-22 12:56:09 -06:00
f6b7583a2a
add tasks for single mode
2020-04-20 12:55:40 -06:00
f76a3090c4
add mcnc big20 test cases and start debugging
2020-04-18 19:25:16 -06:00
2ffd174e6a
fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
2020-04-15 15:48:33 -06:00
23aef96d3a
add behavioral verilog test case to Travis CI
2020-04-12 19:55:47 -06:00
f71a85a1d4
add test cases on different routing multiplexer circuit designs to Travis CI
2020-04-12 15:39:45 -06:00
214d98fbcd
add register chain and scan chain to Travis CI
2020-04-12 15:28:22 -06:00
da5af8f0e0
try to add aib test case. bug found
2020-04-12 14:54:45 -06:00
600a48edc7
add test case of BRAM to Travis CI
2020-04-12 14:27:05 -06:00
49ddbf98c3
add more testing architecture to openfpga_flow
2020-04-11 18:01:09 -06:00
130b78ca74
update arch in openfpga_flow
2020-04-11 18:00:37 -06:00
eb3b02277a
Added XML and benchmarks for testing
2020-04-06 00:32:06 -06:00
tangxifan
ganeshgore