Ganesh Gore
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a6263c44af
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Updated format
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2023-02-11 18:12:04 -07:00 |
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Ganesh Gore
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2afb91596f
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Refactored run_openfpga_task.py
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2023-02-11 18:04:54 -07:00 |
tangxifan
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97c72c73f1
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[test] add a small test to validate tcl integration
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2022-12-02 11:43:46 -08:00 |
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tangxifan
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729a3a0249
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[engine] tcl integration has initial success. Upload example scripts
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2022-12-01 16:31:15 -08:00 |
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tangxifan
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9d8f4c1664
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[script] format python codes
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2022-11-21 14:21:31 -08:00 |
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tangxifan
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abee802830
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[script] now build task_result.csv from openfpgashell.log rather than vpr_stdout.log because of missing block usage numbers
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2022-09-20 13:46:30 -07:00 |
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tangxifan
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373566416c
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Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
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2022-09-16 16:47:21 -07:00 |
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tangxifan
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a8d7b6c2c4
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[script] add a python script for users to visualize the I/O sequence
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2022-09-16 10:49:10 -07:00 |
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tangxifan
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6c44f321e5
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[script] fixed a bug
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2022-08-22 18:24:26 -07:00 |
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tangxifan
|
2bbf2f02c9
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[script] now return status on each arch upgrade task
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2022-08-22 18:23:00 -07:00 |
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tangxifan
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3c9c11d451
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[script] working on formatting
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2022-08-22 18:02:38 -07:00 |
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tangxifan
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55e765a206
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[script] slight improve on formatting
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2022-08-22 18:00:14 -07:00 |
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tangxifan
|
4a7c3fce93
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[script] debugging format
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2022-08-22 17:04:30 -07:00 |
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tangxifan
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2f5ea0cabb
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[script] functional arch file converter; need to clean up formatting issues
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2022-08-22 16:40:49 -07:00 |
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tangxifan
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4efc506762
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[script] now change to use minidom and debugging the child removal
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2022-08-22 16:33:49 -07:00 |
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tangxifan
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880d7122bf
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[script] complete code; start debugging on arch file converter
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2022-08-22 12:29:49 -07:00 |
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tangxifan
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5134ea2233
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[script] save progress
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2022-08-22 11:00:46 -07:00 |
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tangxifan
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a61d6a2685
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[script] developing arch converting script
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2022-08-22 10:34:29 -07:00 |
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tangxifan
|
9ea4a7c90f
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[script] fixed a bug
|
2022-08-01 19:18:41 -07:00 |
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tangxifan
|
55c7b75ab6
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[script] even when power analysis mode is turned off, if users define a act file, still use it
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2022-08-01 18:13:57 -07:00 |
root
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0da44ad1fc
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[script] now .act file is no longer required in openfpga_flow/task when power analysis option is off
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2022-08-02 08:02:28 +08:00 |
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Ganesh Gore
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daae02a614
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Minor documentation update
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2022-05-08 13:03:16 -06:00 |
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tangxifan
|
74045fc7a1
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[Script] Fix a bug
|
2022-02-14 23:11:42 -08:00 |
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tangxifan
|
2990eb7406
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[Script] Fixed a bug in task run when removing previous runs
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2022-02-14 22:54:16 -08:00 |
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tangxifan
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1d3c9ff192
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[Script] Adapt python scripts to support include directory
|
2022-02-01 13:55:25 -08:00 |
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tangxifan
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dd40057992
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[Script] Fixed a bug which causes errors when removing run-directory
|
2022-01-25 13:56:42 -08:00 |
Aram Kostanyan
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758453f725
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Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
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2022-01-21 02:21:00 +05:00 |
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Aram Kostanyan
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588ee14920
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Merge branch 'master' into issue-483
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2022-01-18 13:38:12 +05:00 |
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Aram Kostanyan
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fb2e4377c8
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Added missing changes from previous commit.
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2022-01-17 19:42:40 +05:00 |
|
Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
Awais Abbas
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fc52a4696c
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Yosys only support added in OpenFPGA
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2022-01-06 14:44:11 +05:00 |
nadeemyaseen-rs
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1ea56b2d18
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Merge remote-tracking branch 'upstream/master' into update_from_upstream
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2021-11-18 00:00:55 +05:00 |
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Aram Kostanyan
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a355977420
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Adding Yosys+Verific support.
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2021-10-29 18:34:27 +05:00 |
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nadeemyaseen-rs
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274252438a
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Merge remote-tracking branch 'upstream/master' into update_from_upstream
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2021-10-20 20:13:46 +05:00 |
Christophe Alexandre
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c42acec81e
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Fixing python string formatting: clean_up_and_exit calls in run_fpga_flow.py
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2021-10-18 10:45:35 +00:00 |
|
Christophe Alexandre
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c3dd704bf3
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Fixing typo in run_fpga_flow.py
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2021-10-18 09:13:42 +00:00 |
|
Christophe Alexandre
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d411967159
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Fixing small typo in run_fpga_flow.py
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2021-10-15 10:01:12 +00:00 |
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tangxifan
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6adf439081
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Merge remote-tracking branch 'upstream/master'
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2021-09-01 14:19:00 -07:00 |
Will
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c31c1d8b04
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Accept absolute project paths as inputs to the 'run_fpga_task.py' script.
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2021-08-13 11:08:09 -04:00 |
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tangxifan
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8baf60603a
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[Script] Patching the run_fpga_task.py on pin constraint files
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2021-07-02 15:59:29 -06:00 |
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Ganesh Gore
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c67807868c
|
[bugFix] Benchamrk variable declaration
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2021-07-02 15:26:39 -06:00 |
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Ganesh Gore
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edd5be2cae
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[CI] Added testcase for benchmark variable
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2021-07-02 12:51:34 -06:00 |
|
Ganesh Gore
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1de1f2f2e2
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[FLOW] Variable in capital case
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2021-07-01 22:26:00 -06:00 |
|
Ganesh Gore
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81f9dff9ff
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[Flow] Allows benchmark specific var declaraton
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2021-07-01 22:19:53 -06:00 |
komaljaved-rs
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6559f71082
|
added ci_scripts
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2021-07-01 15:07:37 +05:00 |
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tangxifan
|
7119075253
|
[Script] Remove the post-processing on ``define_simulation.v`` since it is deprecated
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2021-06-29 15:52:42 -06:00 |
|
tangxifan
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fd580bb36f
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[Script] Update script to keep back compatibility: local run directory is different only for those benchmarks sharing the same top module name
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2021-06-22 11:45:23 -06:00 |
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tangxifan
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f9e66e1bae
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[Script] Support benchmarks with same top module names in openfpga flow script; Now each benchmark local run directory has a unique name;
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2021-06-21 15:27:12 -06:00 |
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tangxifan
|
fce84e564d
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[Script] Patch on missing string to show in error message
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2021-06-18 11:20:35 -06:00 |
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tangxifan
|
0e01177cf0
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[Script] Now openfpga flow script output detailed error message when task is not found
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2021-06-18 11:01:45 -06:00 |