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2741 Commits

Author SHA1 Message Date
tangxifan 46b12611a9 [OpenFPGA Tool] Bug fix for smart fast configuration 2020-09-23 22:04:07 -06:00
tangxifan fcf1ff418f [Architecture] Add Verilog for SRAM using set/reset 2020-09-23 21:53:38 -06:00
tangxifan 73e59d67af [Architecture] Add test case for fast configuration using set signals 2020-09-23 21:50:23 -06:00
tangxifan 349aa79069 [Regression test] Add test case for smart fast configuration 2020-09-23 21:49:38 -06:00
tangxifan 9331ef941d [Architecture] Add architecture that use both set and reset signals 2020-09-23 21:46:04 -06:00
tangxifan 7591060fbd [Architecture] Add configurable latch Verilog designs and assoicated architectures 2020-09-23 21:45:06 -06:00
tangxifan 8fa4fa1125 [Architecture] Add openfpga architecture using set signals for configurable latch 2020-09-23 21:39:31 -06:00
tangxifan 154c9045f6 [OpoenFPGA Tool] Bug fix for smart fast configuration 2020-09-23 21:38:42 -06:00
tangxifan c2c37d7555 [OpenFPGA Tool] Add more print-out for smart fast configuration 2020-09-23 21:34:23 -06:00
tangxifan f57fd273af [Documentation] Update documentation for smart fast configuration 2020-09-23 21:28:06 -06:00
tangxifan a3abf81afe [OpenFPGA Tool] Support on set signals and smart selection between reset and set signal for fast configuration 2020-09-23 21:25:06 -06:00
tangxifan 709a20a349 [Regression Test] Deploy new test to CI 2020-09-23 20:45:19 -06:00
tangxifan 05c2e652a4 [Regression Test] Add a new test case for using scan-chain ff in frame-based configuration protocol 2020-09-23 20:44:06 -06:00
tangxifan 2869eae8a9 [Architecture] Add openfpga architecture where scan-chain ff is used in frame-based configuration protocol 2020-09-23 20:43:15 -06:00
tangxifan fc60b18191 [Architecture] Now a regular flip-flop can be used in frame-based configuration 2020-09-23 20:41:49 -06:00
tangxifan 8b8ce22fd1 [OpenFPGA Tool] Bug fix for the edge trigger attribute in cirucit library 2020-09-23 20:37:28 -06:00
tangxifan 3d234d840b [Documentation] Update documentation for the edge triggered attribute 2020-09-23 20:31:11 -06:00
tangxifan 064678fe32 [OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol 2020-09-23 20:27:52 -06:00
tangxifan 8e4e66038a [Architecture] Bug fix for standalone memory 2020-09-23 19:32:48 -06:00
tangxifan 437ef54431 [Regression Test] Bug fix for CI 2020-09-23 19:20:41 -06:00
tangxifan ad881ea4dc [OpenFPGA Tool] Bug fix for Verilog testbench using frame-based /memory bank 2020-09-23 18:59:25 -06:00
tangxifan 129caea38c [Architecture] Patch configurable latch Verilog HDL with resetb 2020-09-23 18:30:48 -06:00
tangxifan 1864b080a2 [Architecture] Bug fix in configurable latch Verilog HDL 2020-09-23 18:28:45 -06:00
tangxifan 9adeb550dc [OpenFPGA Tool] Bug fix in fabric builder 2020-09-23 18:28:00 -06:00
tangxifan 341a757831 [Regression Test] Deploy configuration frame using ccff test case to CI 2020-09-23 18:05:55 -06:00
tangxifan ebb866d04a [Architecture] Patch frame based using ccff 2020-09-23 18:04:14 -06:00
tangxifan 906191e931 [Architecture] Use strict latch Verilog HDL in frame-based procotol 2020-09-23 17:58:13 -06:00
tangxifan 645db17168 [Architecture] Patch DFF Verilog HDL 2020-09-23 17:52:59 -06:00
tangxifan 092ada39f4 [Architecture] Add Verilog HDL for DFF with write enable 2020-09-23 17:49:30 -06:00
tangxifan ad385c6d69 [Regression Test] Add test case for using SRAM cell in frame-based configuration 2020-09-23 17:39:36 -06:00
tangxifan 1a2c66f07d [Architecture] Add openfpga architecture where frame-based configuration procotol uses a SRAM cell 2020-09-23 17:34:49 -06:00
tangxifan f0d31f50f4 [Regression Test] Deploy active-low configurable latch test case to CI 2020-09-23 17:28:36 -06:00
tangxifan a3c982a83f [Architecture] Patch the openfpga architecture using active-low configurable latch 2020-09-23 17:27:16 -06:00
tangxifan f23c25e123 [Regression Test] Add test case for configurable latch with active-low reset 2020-09-23 17:25:17 -06:00
tangxifan a94c2655c2 [Architecture] Patch Verilog HDL for configurable latch 2020-09-23 17:21:30 -06:00
tangxifan 893859be37 [Architecture] Add openfpga architecture using active-low configurable latch 2020-09-23 17:21:00 -06:00
tangxifan b242ab79bd [OpenFPGA Flow] Add Verilog HDL for configurable latch with active-low reset 2020-09-23 17:19:02 -06:00
tangxifan 5c62bafa7f [Regression Test] Deploy the fix device test case to CI 2020-09-23 16:48:45 -06:00
tangxifan 149d5b20bd [Regression Test] Add test case for fixed device support 2020-09-23 16:47:11 -06:00
tangxifan c92cf71891 [Regression Test] Add a new template script for fixed device support 2020-09-23 16:46:41 -06:00
tangxifan 6ed05d380b [Regression Test] Deploy pattern based local routing test case to CI 2020-09-23 16:08:01 -06:00
tangxifan 3350695806 [Regression test] Add test case for pattern based local routing architecture 2020-09-23 16:06:47 -06:00
tangxifan 1aab691e9d [Architecture] Add openfpga architecture using pattern based local routing 2020-09-23 16:06:16 -06:00
tangxifan 951a47b19c [Architecture] Add k4 series architecture using pattern-based local routing 2020-09-23 16:05:39 -06:00
ganeshgore 32c43ffb90 Script cleanup 2020-09-23 14:06:33 -06:00
ganeshgore e31589f9b6 Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev 2020-09-23 14:03:25 -06:00
tangxifan 6480b06a2d [OpenFPGA tool] Remove out-of-data test blif, architecture and scripts 2020-09-23 11:01:53 -06:00
Laboratory for Nano Integrated Systems (LNIS) d32998b9ec
Merge pull request #91 from LNIS-Projects/dev 
[Regression Tests] Remove deadlink
 2020-09-22 23:27:11 -06:00
tangxifan 7729f671ab [Regression Tests] Remove deadlink 2020-09-22 18:35:41 -06:00
Laboratory for Nano Integrated Systems (LNIS) 9515d2310a
Merge pull request #90 from LNIS-Projects/dev 
Architecture and regression test update
 2020-09-22 16:11:06 -06:00