tangxifan
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3afb92d6a5
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[core] code format
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2024-06-30 22:48:15 -07:00 |
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tangxifan
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1fd974d544
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[core] fixed a bug where clock network size cannot impact global port on top module
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2024-06-29 17:35:47 -07:00 |
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tangxifan
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76f446caec
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[core] fixed a bug
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2023-09-25 21:13:11 -07:00 |
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tangxifan
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3adf81046a
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[core] code format
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2023-09-25 17:22:26 -07:00 |
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tangxifan
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5e269e8bc4
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[core] support port merging at grid modules
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2023-09-25 17:21:58 -07:00 |
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tangxifan
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fd99dafad7
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[core] code format
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2023-09-25 16:51:01 -07:00 |
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tangxifan
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96f36a96dd
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[core] syntax
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2023-09-25 16:50:30 -07:00 |
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tangxifan
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ca715f4c82
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[core] developing parser to support subtile port merge
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2023-09-25 16:46:34 -07:00 |
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tangxifan
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60ff298987
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[lib] add new feature to enable clock tree connection to global ports of tiles
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2023-02-28 22:36:41 -08:00 |
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tangxifan
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6d31b319a2
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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tangxifan
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e909f4fabe
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[lib] rename libopenfpga to libs
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2022-08-18 10:27:20 -07:00 |