riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
5,521 Commits 72 Branches 8 Tags 104 MiB
Commit Graph

5521 Commits

Author SHA1 Message Date
Yunus Emre ERYILMAZ f62d435b1e
Update frac_mem_32k.v 2022-10-12 09:35:35 +03:00
dependabot[bot] c45b51a319
Bump yosys-plugins from `27208ce` to `b3430d2` 
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `27208ce` to `b3430d2`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](27208ce082...b3430d2e55)

---
updated-dependencies:
- dependency-name: yosys-plugins
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2022-10-12 06:19:46 +00:00
tangxifan d79ada8720
Merge pull request #837 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-10-07 17:07:08 -07:00
github-actions[bot] 3ffcfb54c9 Updated Patch Count 2022-10-08 00:04:52 +00:00
tangxifan 215d9dfccb
Merge pull request #836 from lnis-uofu/xmllint 
Format architecture XML files
 2022-10-07 13:36:53 -07:00
tangxifan 35869b480a
Merge branch 'master' into xmllint 2022-10-07 10:47:43 -07:00
tangxifan 6e2040f678
Merge pull request #835 from mustafaarslan0/patch-1 
Update k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
 2022-10-07 10:44:15 -07:00
tangxifan 1abdb56609 [script] make xmllint indent specific to two space 2022-10-07 10:33:59 -07:00
tangxifan 85089cbc88 [arch] apply xml format for all the architecture files 2022-10-07 10:31:51 -07:00
tangxifan d6dd540541 [script] enable inplace for xml formatting 2022-10-07 10:28:47 -07:00
tangxifan 5e220048ab [ci] add XML lint to dependency; enable xml format in CI 2022-10-07 10:21:14 -07:00
tangxifan 6c12e8dc24 [script] developing xml formatting command 2022-10-07 10:16:00 -07:00
tangxifan 4d4ab60fe4 [ci] rename workflow 2022-10-07 10:12:40 -07:00
mustafa.arslan 508c01cef6
Update k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml 
Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
 2022-10-07 09:38:07 +03:00
tangxifan ae708c987f
Merge pull request #834 from lnis-uofu/code_format 
Now C/C++ codes follow a clang format
 2022-10-06 22:35:19 -07:00
tangxifan 6de0cb86b3 [ci] bug fix 2022-10-06 20:49:38 -07:00
tangxifan df106d9bef [ci] added a workflow to check code format 2022-10-06 19:21:25 -07:00
tangxifan 08e88b1b4c [script] debugging check format script 2022-10-06 19:13:13 -07:00
tangxifan 5d9e918d5d [ci] enable check C/C++ format on CI 2022-10-06 18:26:06 -07:00
tangxifan afdc071c4c [engine] apply code format 2022-10-06 18:13:33 -07:00
tangxifan e2debd2dde [engine] add missing header files after coding formatter sorts the include files 2022-10-06 18:08:57 -07:00
tangxifan 503b95343d Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into code_format 2022-10-06 17:54:48 -07:00
tangxifan 2a3417163e
Merge pull request #833 from lnis-uofu/vtr_dependabot 
Enabled dependabot for VTR submodule
 2022-10-06 17:54:31 -07:00
tangxifan 6d31b319a2 [engine] update source files subject to code formatting rules 2022-10-06 17:08:50 -07:00
tangxifan b8c59db9e9 [script] debugging cmake format 2022-10-06 17:07:57 -07:00
tangxifan d3e374fe57 [script] debugging make format 2022-10-06 17:04:30 -07:00
tangxifan 110b27b3fc [script] now top-level makefile can do ``make format`` for C/C++ files 2022-10-06 16:59:15 -07:00
tangxifan 6230196c21 [ci] add C/C++ code format style file 2022-10-06 16:44:05 -07:00
tangxifan 4c707d1eae [vtr] update vtr 2022-10-06 14:27:15 -07:00
tangxifan 608c43d05b [ci] enable dependabot for vtr 2022-10-06 14:26:11 -07:00
tangxifan 10267500be
Merge pull request #826 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-10-04 16:38:20 -07:00
github-actions[bot] 73b1669a41 Updated Patch Count 2022-10-04 23:32:50 +00:00
tangxifan 46044d5217
Merge pull request #824 from lnis-uofu/place_rr_graph 
Fix a bug where placer does not call tileable rr-graph generator
 2022-10-04 12:08:56 -07:00
tangxifan ab53f88c2b [test] now use a fixed device layout for the single-mode LUT design testcase 2022-10-04 10:05:22 -07:00
tangxifan 3a3877fd08 [engine] update vtr: fix a bug where placer does not call tileable rr_graph generator 2022-10-03 21:18:08 -07:00
tangxifan b652bc8d51
Merge pull request #823 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-10-03 13:32:01 -07:00
github-actions[bot] 8b63f93e9f Updated Patch Count 2022-10-03 20:29:52 +00:00
tangxifan 62511f4792
Merge pull request #822 from lnis-uofu/cmake_flag 
New option to bypass version build
 2022-10-03 13:28:56 -07:00
tangxifan b26b0ce8d8 [ci] deploy no version number build test to ci 2022-10-03 11:48:19 -07:00
tangxifan cc6bf85433 [cmake] now rename version to short 'OPENFPGA_ENABLE_VERSION' 2022-10-03 11:37:41 -07:00
tangxifan a144794ce6 [cmake] skip custom build on version build with an option 2022-10-03 11:18:43 -07:00
tangxifan 81e524cec4 [CMake] Added a new option 'OPENFPGA_WITH_VERSION_UP_TO_DATE' which allows users to skip version build (by default it remains always on) 2022-10-03 11:11:21 -07:00
tangxifan db7a052a2b
Merge pull request #820 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-10-01 18:59:16 -07:00
github-actions[bot] fe26429c86 Updated Patch Count 2022-10-02 00:04:53 +00:00
tangxifan 30c5569e0f
Merge pull request #819 from lnis-uofu/gsb_cout_bug 
Fixed a bug where pins for direct connections between programmable blocks appears in GSB/Routing blocks
 2022-10-01 14:59:36 -07:00
tangxifan 13c819bb28 [ci] deply new test to ci 2022-10-01 11:04:08 -07:00
tangxifan 4eaecde0b9 [test] add golden netlists to ensure no cout in gsb 2022-10-01 11:03:13 -07:00
tangxifan 78f30cf072 [test] add a new test to track the golden netlists where cout is not in GSB 2022-09-30 15:38:27 -07:00
tangxifan 1c7d5a05b4 [engine] update vtr 2022-09-30 15:26:59 -07:00
tangxifan 0d8d8446ee [test] fixed a bug where OPIN for direct connection is included in GSB 2022-09-30 15:24:51 -07:00