Merge pull request #819 from lnis-uofu/gsb_cout_bug
Fixed a bug where pins for direct connections between programmable blocks appears in GSB/Routing blocks
This commit is contained in:
tangxifan
GitHub
commit
30c5569e0f
|
|
@ -256,44 +256,24 @@ RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
|
|||
|
||||
/* Fill opin_rr_nodes */
|
||||
/* Copy from temp_opin_rr_node to opin_rr_node */
|
||||
for (const RRNodeId& inode : temp_opin_rr_nodes[0]) {
|
||||
/* Skip those has no configurable outgoing, they should NOT appear in the GSB connection
|
||||
* This is for those grid output pins used by direct connections
|
||||
*/
|
||||
if (0 == std::distance(vpr_device_ctx.rr_graph.node_configurable_out_edges(inode).begin(),
|
||||
vpr_device_ctx.rr_graph.node_configurable_out_edges(inode).end())) {
|
||||
continue;
|
||||
for (size_t opin_array_id = 0; opin_array_id < temp_opin_rr_nodes.size(); ++opin_array_id) {
|
||||
for (const RRNodeId& inode : temp_opin_rr_nodes[opin_array_id]) {
|
||||
/* Skip those has no configurable outgoing, they should NOT appear in the GSB connection
|
||||
* This is for those grid output pins used by direct connections
|
||||
*/
|
||||
if (0 == vpr_device_ctx.rr_graph.num_configurable_edges(inode)) {
|
||||
continue;
|
||||
}
|
||||
/* Do not consider OPINs that directly drive an IPIN
|
||||
* they are supposed to be handled by direct connection
|
||||
*/
|
||||
if (true == is_opin_direct_connected_ipin(vpr_device_ctx.rr_graph, inode)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Grid[x+1][y+1] Bottom side outputs pins */
|
||||
rr_gsb.add_opin_node(inode, side_manager.get_side());
|
||||
}
|
||||
|
||||
/* Do not consider OPINs that directly drive an IPIN
|
||||
* they are supposed to be handled by direct connection
|
||||
*/
|
||||
if (true == is_opin_direct_connected_ipin(vpr_device_ctx.rr_graph, inode)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Grid[x+1][y+1] Bottom side outputs pins */
|
||||
rr_gsb.add_opin_node(inode, side_manager.get_side());
|
||||
}
|
||||
|
||||
for (const RRNodeId& inode : temp_opin_rr_nodes[1]) {
|
||||
/* Skip those has no configurable outgoing, they should NOT appear in the GSB connection
|
||||
* This is for those grid output pins used by direct connections
|
||||
*/
|
||||
if (0 == std::distance(vpr_device_ctx.rr_graph.node_configurable_out_edges(inode).begin(),
|
||||
vpr_device_ctx.rr_graph.node_configurable_out_edges(inode).end())) {
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Do not consider OPINs that directly drive an IPIN
|
||||
* they are supposed to be handled by direct connection
|
||||
*/
|
||||
if (true == is_opin_direct_connected_ipin(vpr_device_ctx.rr_graph, inode)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Grid[x+1][y] TOP side outputs pins */
|
||||
rr_gsb.add_opin_node(inode, side_manager.get_side());
|
||||
}
|
||||
|
||||
/* Clean ipin_rr_nodes */
|
||||
|
|
@ -375,8 +355,7 @@ RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
|
|||
/* Skip those has no configurable outgoing, they should NOT appear in the GSB connection
|
||||
* This is for those grid output pins used by direct connections
|
||||
*/
|
||||
if (0 == std::distance(vpr_device_ctx.rr_graph.node_configurable_in_edges(inode).begin(),
|
||||
vpr_device_ctx.rr_graph.node_configurable_in_edges(inode).end())) {
|
||||
if (0 == vpr_device_ctx.rr_graph.node_configurable_in_edges(inode).size()) {
|
||||
continue;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,255 @@
|
|||
<!-- Architecture annotation for OpenFPGA framework
|
||||
This annotation supports the k6_N10_40nm.xml
|
||||
- General purpose logic block
|
||||
- K = 6, N = 10, I = 40
|
||||
- Single mode
|
||||
- Routing architecture
|
||||
- L = 4, fc_in = 0.15, fc_out = 0.1
|
||||
-->
|
||||
<openfpga_architecture>
|
||||
<technology_library>
|
||||
<device_library>
|
||||
<device_model name="logic" type="transistor">
|
||||
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||
<design vdd="0.9" pn_ratio="2"/>
|
||||
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||
</device_model>
|
||||
<device_model name="io" type="transistor">
|
||||
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||
<design vdd="2.5" pn_ratio="3"/>
|
||||
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||
</device_model>
|
||||
</device_library>
|
||||
<variation_library>
|
||||
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||
</variation_library>
|
||||
</technology_library>
|
||||
<circuit_library>
|
||||
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
|
||||
<design_technology type="cmos" topology="inverter" size="1"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
|
||||
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
|
||||
<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
|
||||
<design_technology type="cmos" topology="OR"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="a" size="1"/>
|
||||
<port type="input" prefix="b" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="a b" out_port="out">
|
||||
10e-12 5e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="a b" out_port="out">
|
||||
10e-12 5e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
|
||||
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="input" prefix="sel" size="1"/>
|
||||
<port type="input" prefix="selb" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in sel selb" out_port="out">
|
||||
10e-12 5e-12 5e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in sel selb" out_port="out">
|
||||
10e-12 5e-12 5e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
|
||||
</circuit_model>
|
||||
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
|
||||
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="openfpga_flow/openfpga_cell_library/verilog/dff.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="D" size="1"/>
|
||||
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
|
||||
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
|
||||
<port type="output" prefix="Q" size="1"/>
|
||||
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
|
||||
</circuit_model>
|
||||
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" fracturable_lut="true"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
|
||||
<lut_input_buffer exist="true" circuit_model_name="buf4"/>
|
||||
<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="OR2"/>
|
||||
<port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
|
||||
<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
|
||||
<port type="sram" prefix="sram" size="16"/>
|
||||
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
|
||||
</circuit_model>
|
||||
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
|
||||
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="openfpga_flow/openfpga_cell_library/verilog/dff.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
|
||||
<port type="input" prefix="D" size="1"/>
|
||||
<port type="output" prefix="Q" size="1"/>
|
||||
<port type="output" prefix="QN" size="1"/>
|
||||
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="openfpga_flow/openfpga_cell_library/verilog/gpio.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
|
||||
<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
|
||||
<port type="input" prefix="outpad" lib_name="A" size="1"/>
|
||||
<port type="output" prefix="inpad" lib_name="Y" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="openfpga_flow/openfpga_cell_library/spice/adder.sp" verilog_netlist="openfpga_flow/openfpga_cell_library/verilog/adder.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="a" lib_name="A" size="1"/>
|
||||
<port type="input" prefix="b" lib_name="B" size="1"/>
|
||||
<port type="input" prefix="cin" lib_name="CI" size="1"/>
|
||||
<port type="output" prefix="sumout" lib_name="SUM" size="1"/>
|
||||
<port type="output" prefix="cout" lib_name="CO" size="1"/>
|
||||
</circuit_model>
|
||||
</circuit_library>
|
||||
<configuration_protocol>
|
||||
<organization type="scan_chain" circuit_model_name="DFFR"/>
|
||||
</configuration_protocol>
|
||||
<connection_block>
|
||||
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
|
||||
</connection_block>
|
||||
<switch_block>
|
||||
<switch name="0" circuit_model_name="mux_2level_tapbuf"/>
|
||||
</switch_block>
|
||||
<routing_segment>
|
||||
<segment name="L4" circuit_model_name="chan_segment"/>
|
||||
</routing_segment>
|
||||
<direct_connection>
|
||||
<!-- direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/-->
|
||||
<direct name="adder_carry" circuit_model_name="direct_interc"/>
|
||||
</direct_connection>
|
||||
<pb_type_annotations>
|
||||
<!-- physical pb_type binding in complex block IO -->
|
||||
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
|
||||
<pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
|
||||
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
|
||||
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
|
||||
<!-- End physical pb_type binding in complex block IO -->
|
||||
|
||||
<!-- physical pb_type binding in complex block CLB -->
|
||||
<!-- physical mode will be the default mode if not specified -->
|
||||
<pb_type name="clb">
|
||||
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
|
||||
<interconnect name="crossbar" circuit_model_name="mux_2level"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle" physical_mode_name="physical"/>
|
||||
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
|
||||
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
|
||||
<pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="ADDF"/>
|
||||
<!-- Binding operating pb_type to physical pb_type -->
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
|
||||
<!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
|
||||
<port name="in" physical_mode_port="in[0:2]"/>
|
||||
<port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
|
||||
<!-- Binding operating pb_types in mode 'arithmetic' -->
|
||||
<pb_type name="clb.fle[arithmetic].arithmetic.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
|
||||
<!-- Binding the lut4 to the first 3 inputs of fracturable lut6 -->
|
||||
<port name="in" physical_mode_port="in[0:2]"/>
|
||||
<port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
|
||||
<pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
|
||||
<!-- Binding operating pb_types in mode 'ble4' -->
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
|
||||
<!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
|
||||
<port name="in" physical_mode_port="in[0:3]"/>
|
||||
<port name="out" physical_mode_port="lut4_out"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||
<!-- End physical pb_type binding in complex block IO -->
|
||||
</pb_type_annotations>
|
||||
</openfpga_architecture>
|
||||
|
|
@ -207,7 +207,8 @@
|
|||
<segment name="L4" circuit_model_name="chan_segment"/>
|
||||
</routing_segment>
|
||||
<direct_connection>
|
||||
<direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
|
||||
<!-- direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/-->
|
||||
<direct name="adder_carry" circuit_model_name="direct_interc"/>
|
||||
</direct_connection>
|
||||
<pb_type_annotations>
|
||||
<!-- physical pb_type binding in complex block IO -->
|
||||
|
|
|
|||
|
|
@ -199,6 +199,7 @@ run-task _task_copy $@
|
|||
echo -e "Testing output files without time stamp";
|
||||
run-task basic_tests/no_time_stamp/device_1x1 $@
|
||||
run-task basic_tests/no_time_stamp/device_4x4 $@
|
||||
run-task basic_tests/no_time_stamp/no_cout_in_gsb $@
|
||||
# Run git-diff to ensure no changes on the golden netlists
|
||||
# Switch to root path in case users are running the tests in another location
|
||||
cd ${OPENFPGA_PATH}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,36 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Configuration file for running experiments
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||
# timeout_each_job is timeout for each job
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
[GENERAL]
|
||||
run_engine=openfpga_shell
|
||||
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||
power_analysis = true
|
||||
spice_output=false
|
||||
verilog_output=true
|
||||
timeout_each_job = 20*60
|
||||
fpga_flow=yosys_vpr
|
||||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga
|
||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_abspath_openfpga.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||
openfpga_vpr_device_layout = 2x2
|
||||
openfpga_vpr_route_chan_width = 20
|
||||
openfpga_output_dir=${PATH:TASK_DIR}/golden_outputs_no_time_stamp
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench_read_verilog_options_common = -nolatches
|
||||
bench0_top = and2
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
|
|
@ -0,0 +1,126 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: FPGA Verilog Testbench for Formal Top-level netlist of Design: and2
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
module and2_top_formal_verification_random_tb;
|
||||
// ----- Default clock port is added here since benchmark does not contain one -------
|
||||
reg [0:0] clk;
|
||||
|
||||
// ----- Shared inputs -------
|
||||
reg [0:0] a;
|
||||
reg [0:0] b;
|
||||
|
||||
// ----- FPGA fabric outputs -------
|
||||
wire [0:0] c_gfpga;
|
||||
|
||||
// ----- Benchmark outputs -------
|
||||
wire [0:0] c_bench;
|
||||
|
||||
// ----- Output vectors checking flags -------
|
||||
reg [0:0] c_flag;
|
||||
|
||||
// ----- Error counter -------
|
||||
integer nb_error= 0;
|
||||
|
||||
// ----- FPGA fabric instanciation -------
|
||||
and2_top_formal_verification FPGA_DUT(
|
||||
.a(a),
|
||||
.b(b),
|
||||
.c(c_gfpga)
|
||||
);
|
||||
// ----- End FPGA Fabric Instanication -------
|
||||
|
||||
// ----- Reference Benchmark Instanication -------
|
||||
and2 REF_DUT(
|
||||
.a(a),
|
||||
.b(b),
|
||||
.c(c_bench)
|
||||
);
|
||||
// ----- End reference Benchmark Instanication -------
|
||||
|
||||
// ----- Clock 'clk' Initialization -------
|
||||
initial begin
|
||||
clk[0] <= 1'b0;
|
||||
while(1) begin
|
||||
#0.5561901927
|
||||
clk[0] <= !clk[0];
|
||||
end
|
||||
end
|
||||
|
||||
// ----- Begin reset signal generation -----
|
||||
// ----- End reset signal generation -----
|
||||
|
||||
// ----- Input Initialization -------
|
||||
initial begin
|
||||
a <= 1'b0;
|
||||
b <= 1'b0;
|
||||
|
||||
c_flag[0] <= 1'b0;
|
||||
end
|
||||
|
||||
// ----- Input Stimulus -------
|
||||
always@(negedge clk[0]) begin
|
||||
a <= $random;
|
||||
b <= $random;
|
||||
end
|
||||
|
||||
// ----- Begin checking output vectors -------
|
||||
// ----- Skip the first falling edge of clock, it is for initialization -------
|
||||
reg [0:0] sim_start;
|
||||
|
||||
always@(negedge clk[0]) begin
|
||||
if (1'b1 == sim_start[0]) begin
|
||||
sim_start[0] <= ~sim_start[0];
|
||||
end else
|
||||
begin
|
||||
if(!(c_gfpga === c_bench) && !(c_bench === 1'bx)) begin
|
||||
c_flag <= 1'b1;
|
||||
end else begin
|
||||
c_flag<= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge c_flag) begin
|
||||
if(c_flag) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on c_gfpga at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// ----- Begin output waveform to VCD file-------
|
||||
initial begin
|
||||
$dumpfile("and2_formal.vcd");
|
||||
$dumpvars(1, and2_top_formal_verification_random_tb);
|
||||
end
|
||||
// ----- END output waveform to VCD file -------
|
||||
|
||||
initial begin
|
||||
sim_start[0] <= 1'b1;
|
||||
$timeformat(-9, 2, "ns", 20);
|
||||
$display("Simulation start");
|
||||
// ----- Can be changed by the user for his/her need -------
|
||||
#7.786663055
|
||||
if(nb_error == 0) begin
|
||||
$display("Simulation Succeed");
|
||||
end else begin
|
||||
$display("Simulation Failed with %d error(s)", nb_error);
|
||||
end
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for and2_top_formal_verification_random_tb -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,16 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Netlist Summary
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ------ Include fabric top-level netlists -----
|
||||
`include "fabric_netlists.v"
|
||||
|
||||
`include "and2_output_verilog.v"
|
||||
|
||||
`include "and2_top_formal_verification.v"
|
||||
`include "and2_formal_random_top_tb.v"
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,80 @@
|
|||
<!--
|
||||
- Report Bitstream Distribution
|
||||
-->
|
||||
|
||||
<bitstream_distribution>
|
||||
<regions>
|
||||
<region id="0" number_of_bits="2372">
|
||||
</region>
|
||||
</regions>
|
||||
<blocks>
|
||||
<block name="fpga_top" number_of_bits="2372">
|
||||
<block name="grid_clb_1__1_" number_of_bits="296">
|
||||
</block>
|
||||
<block name="grid_clb_1__2_" number_of_bits="296">
|
||||
</block>
|
||||
<block name="grid_clb_2__1_" number_of_bits="296">
|
||||
</block>
|
||||
<block name="grid_clb_2__2_" number_of_bits="296">
|
||||
</block>
|
||||
<block name="grid_io_top_1__3_" number_of_bits="8">
|
||||
</block>
|
||||
<block name="grid_io_top_2__3_" number_of_bits="8">
|
||||
</block>
|
||||
<block name="grid_io_right_3__2_" number_of_bits="8">
|
||||
</block>
|
||||
<block name="grid_io_right_3__1_" number_of_bits="8">
|
||||
</block>
|
||||
<block name="grid_io_bottom_2__0_" number_of_bits="8">
|
||||
</block>
|
||||
<block name="grid_io_bottom_1__0_" number_of_bits="8">
|
||||
</block>
|
||||
<block name="grid_io_left_0__1_" number_of_bits="8">
|
||||
</block>
|
||||
<block name="grid_io_left_0__2_" number_of_bits="8">
|
||||
</block>
|
||||
<block name="sb_0__0_" number_of_bits="36">
|
||||
</block>
|
||||
<block name="sb_0__1_" number_of_bits="68">
|
||||
</block>
|
||||
<block name="sb_0__2_" number_of_bits="32">
|
||||
</block>
|
||||
<block name="sb_1__0_" number_of_bits="72">
|
||||
</block>
|
||||
<block name="sb_1__1_" number_of_bits="96">
|
||||
</block>
|
||||
<block name="sb_1__2_" number_of_bits="66">
|
||||
</block>
|
||||
<block name="sb_2__0_" number_of_bits="40">
|
||||
</block>
|
||||
<block name="sb_2__1_" number_of_bits="78">
|
||||
</block>
|
||||
<block name="sb_2__2_" number_of_bits="36">
|
||||
</block>
|
||||
<block name="cbx_1__0_" number_of_bits="60">
|
||||
</block>
|
||||
<block name="cbx_1__1_" number_of_bits="12">
|
||||
</block>
|
||||
<block name="cbx_1__2_" number_of_bits="48">
|
||||
</block>
|
||||
<block name="cbx_2__0_" number_of_bits="60">
|
||||
</block>
|
||||
<block name="cbx_2__1_" number_of_bits="12">
|
||||
</block>
|
||||
<block name="cbx_2__2_" number_of_bits="48">
|
||||
</block>
|
||||
<block name="cby_0__1_" number_of_bits="54">
|
||||
</block>
|
||||
<block name="cby_0__2_" number_of_bits="54">
|
||||
</block>
|
||||
<block name="cby_1__1_" number_of_bits="42">
|
||||
</block>
|
||||
<block name="cby_1__2_" number_of_bits="42">
|
||||
</block>
|
||||
<block name="cby_2__1_" number_of_bits="84">
|
||||
</block>
|
||||
<block name="cby_2__2_" number_of_bits="84">
|
||||
</block>
|
||||
</block>
|
||||
</blocks>
|
||||
</bitstream_distribution>
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_11_[0] 7.247000222e-11
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__2_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[0] -to fpga_top/cbx_1__2_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[0] -to fpga_top/cbx_1__2_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[1] -to fpga_top/cbx_1__2_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[1] -to fpga_top/cbx_1__2_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[2] -to fpga_top/cbx_1__2_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[2] -to fpga_top/cbx_1__2_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[3] -to fpga_top/cbx_1__2_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[3] -to fpga_top/cbx_1__2_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[4] -to fpga_top/cbx_1__2_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[4] -to fpga_top/cbx_1__2_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[5] -to fpga_top/cbx_1__2_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[5] -to fpga_top/cbx_1__2_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[6] -to fpga_top/cbx_1__2_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[6] -to fpga_top/cbx_1__2_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[7] -to fpga_top/cbx_1__2_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[7] -to fpga_top/cbx_1__2_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[8] -to fpga_top/cbx_1__2_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[8] -to fpga_top/cbx_1__2_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[9] -to fpga_top/cbx_1__2_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[9] -to fpga_top/cbx_1__2_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[0] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[0] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[5] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[5] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[1] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[1] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[6] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[6] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[2] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[2] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[7] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[7] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[3] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[3] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[8] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[8] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[4] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[4] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[9] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[9] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[0] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[0] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[5] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[5] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[1] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[1] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[6] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[6] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[2] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[2] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_left_in[7] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cbx_1__2_/chanx_right_in[7] -to fpga_top/cbx_1__2_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_0__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_2__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[0] -to fpga_top/cby_2__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[0] -to fpga_top/cby_2__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[1] -to fpga_top/cby_2__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[1] -to fpga_top/cby_2__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[2] -to fpga_top/cby_2__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[2] -to fpga_top/cby_2__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[3] -to fpga_top/cby_2__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[3] -to fpga_top/cby_2__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[4] -to fpga_top/cby_2__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[4] -to fpga_top/cby_2__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[5] -to fpga_top/cby_2__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[5] -to fpga_top/cby_2__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[6] -to fpga_top/cby_2__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[6] -to fpga_top/cby_2__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[7] -to fpga_top/cby_2__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[7] -to fpga_top/cby_2__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[8] -to fpga_top/cby_2__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[8] -to fpga_top/cby_2__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[9] -to fpga_top/cby_2__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[9] -to fpga_top/cby_2__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[0] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[0] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[5] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[5] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[1] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[1] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[6] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[6] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[2] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[2] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[7] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[7] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[3] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[3] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[8] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[8] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[4] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[4] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[9] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[9] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[0] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[0] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[5] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[5] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[1] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[1] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[6] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[6] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[2] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[2] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[7] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[7] -to fpga_top/cby_2__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[3] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[3] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[8] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[8] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[4] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[4] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[9] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[9] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[0] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[0] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[5] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[5] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[1] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[1] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[6] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[6] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[2] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[2] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[7] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[7] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[3] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[3] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_bottom_in[8] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_top/cby_2__1_/chany_top_in[8] -to fpga_top/cby_2__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,142 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable configurable memory outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_DFFR_mem/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_DFFR_mem/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mem_frac_logic_out_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mem_frac_logic_out_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_fabric_out_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_fabric_out_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_ff_*_D_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_ff_*_D_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
|
||||
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
|
||||
|
|
@ -0,0 +1,140 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable configuration outputs of all the programmable cells for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/sram
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/sram_inv
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/mode
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/mode_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/sram
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/sram
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/sram
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/sram
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/sram
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/sram
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/sram
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/sram_inv
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/sram_inv
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/sram_inv
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/sram_inv
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/sram_inv
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/sram_inv
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/sram_inv
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/sram
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/sram_inv
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mux_fle_*_in_*/sram
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mux_fle_*_in_*/sram_inv
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/sram
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/sram_inv
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/sram
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/sram
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/sram_inv
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/sram_inv
|
||||
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_*_/DIR
|
||||
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_*_/DIR
|
||||
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_*_/DIR
|
||||
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_*_/DIR
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable routing multiplexer outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/out
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/out
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/out
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/out
|
||||
set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/out
|
||||
set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mux_fle_*_in_*/out
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/out
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/out
|
||||
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/out
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable Switch Block outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_top/sb_*__*_/ccff_tail
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,71 @@
|
|||
<!--
|
||||
- FPGA Fabric I/O Information
|
||||
- Generated by OpenFPGA
|
||||
-->
|
||||
|
||||
<io_coordinates>
|
||||
<io pad="gfpga_pad_GPIO_PAD[48]" x="0" y="1" z="0"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[49]" x="0" y="1" z="1"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[50]" x="0" y="1" z="2"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[51]" x="0" y="1" z="3"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[52]" x="0" y="1" z="4"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[53]" x="0" y="1" z="5"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[54]" x="0" y="1" z="6"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[55]" x="0" y="1" z="7"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[56]" x="0" y="2" z="0"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[57]" x="0" y="2" z="1"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[58]" x="0" y="2" z="2"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[59]" x="0" y="2" z="3"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[60]" x="0" y="2" z="4"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[61]" x="0" y="2" z="5"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[62]" x="0" y="2" z="6"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[63]" x="0" y="2" z="7"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[40]" x="1" y="0" z="0"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[41]" x="1" y="0" z="1"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[42]" x="1" y="0" z="2"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[43]" x="1" y="0" z="3"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[44]" x="1" y="0" z="4"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[45]" x="1" y="0" z="5"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[46]" x="1" y="0" z="6"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[47]" x="1" y="0" z="7"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[0]" x="1" y="3" z="0"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[1]" x="1" y="3" z="1"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[2]" x="1" y="3" z="2"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[3]" x="1" y="3" z="3"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[4]" x="1" y="3" z="4"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[5]" x="1" y="3" z="5"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[6]" x="1" y="3" z="6"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[7]" x="1" y="3" z="7"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[32]" x="2" y="0" z="0"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[33]" x="2" y="0" z="1"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[34]" x="2" y="0" z="2"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[35]" x="2" y="0" z="3"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[36]" x="2" y="0" z="4"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[37]" x="2" y="0" z="5"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[38]" x="2" y="0" z="6"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[39]" x="2" y="0" z="7"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[8]" x="2" y="3" z="0"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[9]" x="2" y="3" z="1"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[10]" x="2" y="3" z="2"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[11]" x="2" y="3" z="3"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[12]" x="2" y="3" z="4"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[13]" x="2" y="3" z="5"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[14]" x="2" y="3" z="6"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[15]" x="2" y="3" z="7"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[24]" x="3" y="1" z="0"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[25]" x="3" y="1" z="1"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[26]" x="3" y="1" z="2"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[27]" x="3" y="1" z="3"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[28]" x="3" y="1" z="4"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[29]" x="3" y="1" z="5"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[30]" x="3" y="1" z="6"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[31]" x="3" y="1" z="7"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[16]" x="3" y="2" z="0"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[17]" x="3" y="2" z="1"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[18]" x="3" y="2" z="2"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[19]" x="3" y="2" z="3"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[20]" x="3" y="2" z="4"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[21]" x="3" y="2" z="5"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[22]" x="3" y="2" z="6"/>
|
||||
<io pad="gfpga_pad_GPIO_PAD[23]" x="3" y="2" z="7"/>
|
||||
</io_coordinates>
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Fabric Netlist Summary
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ------ Include defines: preproc flags -----
|
||||
`include "fpga_defines.v"
|
||||
|
||||
// ------ Include user-defined netlists -----
|
||||
`include "openfpga_flow/openfpga_cell_library/verilog/dff.v"
|
||||
`include "openfpga_flow/openfpga_cell_library/verilog/gpio.v"
|
||||
`include "openfpga_flow/openfpga_cell_library/verilog/adder.v"
|
||||
// ------ Include primitive module netlists -----
|
||||
`include "sub_module/inv_buf_passgate.v"
|
||||
`include "sub_module/arch_encoder.v"
|
||||
`include "sub_module/local_encoder.v"
|
||||
`include "sub_module/mux_primitives.v"
|
||||
`include "sub_module/muxes.v"
|
||||
`include "sub_module/luts.v"
|
||||
`include "sub_module/wires.v"
|
||||
`include "sub_module/memories.v"
|
||||
`include "sub_module/shift_register_banks.v"
|
||||
|
||||
// ------ Include logic block netlists -----
|
||||
`include "lb/logical_tile_io_mode_physical__iopad.v"
|
||||
`include "lb/logical_tile_io_mode_io_.v"
|
||||
`include "lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v"
|
||||
`include "lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v"
|
||||
`include "lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v"
|
||||
`include "lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v"
|
||||
`include "lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v"
|
||||
`include "lb/logical_tile_clb_mode_default__fle.v"
|
||||
`include "lb/logical_tile_clb_mode_clb_.v"
|
||||
`include "lb/grid_io_top.v"
|
||||
`include "lb/grid_io_right.v"
|
||||
`include "lb/grid_io_bottom.v"
|
||||
`include "lb/grid_io_left.v"
|
||||
`include "lb/grid_clb.v"
|
||||
|
||||
// ------ Include routing module netlists -----
|
||||
`include "routing/sb_0__0_.v"
|
||||
`include "routing/sb_0__1_.v"
|
||||
`include "routing/sb_0__2_.v"
|
||||
`include "routing/sb_1__0_.v"
|
||||
`include "routing/sb_1__1_.v"
|
||||
`include "routing/sb_1__2_.v"
|
||||
`include "routing/sb_2__0_.v"
|
||||
`include "routing/sb_2__1_.v"
|
||||
`include "routing/sb_2__2_.v"
|
||||
`include "routing/cbx_1__0_.v"
|
||||
`include "routing/cbx_1__1_.v"
|
||||
`include "routing/cbx_1__2_.v"
|
||||
`include "routing/cby_0__1_.v"
|
||||
`include "routing/cby_1__1_.v"
|
||||
`include "routing/cby_2__1_.v"
|
||||
|
||||
// ------ Include fabric top-level netlists -----
|
||||
`include "fpga_top.v"
|
||||
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Preprocessing flags to enable/disable features in FPGA Verilog modules
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
`define ENABLE_TIMING 1
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,21 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Clock contraints for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
##################################################
|
||||
# Create clock
|
||||
##################################################
|
||||
create_clock -name clk[0] -period 1.11238041e-09 -waveform {0 5.56190205e-10} [get_ports {clk[0]}]
|
||||
##################################################
|
||||
# Create programmable clock
|
||||
##################################################
|
||||
create_clock -name prog_clk[0] -period 9.999999939e-09 -waveform {0 4.99999997e-09} [get_ports {prog_clk[0]}]
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
<rr_cb x="0" y="0" num_sides="4">
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
<rr_cb x="0" y="1" num_sides="4">
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
<rr_cb x="0" y="2" num_sides="4">
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
<rr_cb x="1" y="0" num_sides="4">
|
||||
<IPIN side="top" index="0" node_id="124" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="396" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="397" index="1" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="1" node_id="125" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="398" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="399" index="3" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="2" node_id="126" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="400" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="401" index="5" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="3" node_id="127" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="402" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="403" index="7" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="4" node_id="128" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="404" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="405" index="9" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="5" node_id="129" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="406" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="407" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="0" node_id="24" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="398" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="399" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="408" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="409" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="1" node_id="25" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="400" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="401" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="410" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="411" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="2" node_id="26" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="402" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="403" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="412" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="413" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="3" node_id="27" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="404" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="405" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="414" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="415" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="4" node_id="28" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="396" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="397" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="406" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="407" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="5" node_id="29" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="398" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="399" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="408" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="409" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="6" node_id="30" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="400" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="401" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="410" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="411" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="7" node_id="31" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="402" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="403" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="412" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="413" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
<rr_cb x="1" y="1" num_sides="4">
|
||||
<IPIN side="top" index="0" node_id="258" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="422" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="423" index="1" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="1" node_id="259" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="424" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="425" index="3" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="2" node_id="260" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="426" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="427" index="5" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="3" node_id="261" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="428" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="429" index="7" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="4" node_id="262" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="430" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="431" index="9" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="5" node_id="263" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="432" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="433" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
<rr_cb x="1" y="2" num_sides="4">
|
||||
<IPIN side="top" index="0" node_id="356" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="448" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="449" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="458" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="459" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="1" node_id="357" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="450" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="451" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="460" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="461" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="2" node_id="358" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="452" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="453" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="462" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="463" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="3" node_id="359" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="454" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="455" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="464" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="465" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="4" node_id="360" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="456" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="457" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="466" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="467" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="5" node_id="361" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="448" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="449" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="458" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="459" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="6" node_id="362" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="450" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="451" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="460" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="461" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="7" node_id="363" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="452" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="453" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="462" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="463" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
<rr_cb x="2" y="0" num_sides="4">
|
||||
<IPIN side="top" index="0" node_id="159" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="416" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="399" index="1" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="1" node_id="160" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="396" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="401" index="3" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="2" node_id="161" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="398" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="403" index="5" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="3" node_id="162" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="400" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="417" index="7" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="4" node_id="163" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="418" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="407" index="9" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="5" node_id="164" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="404" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="409" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="0" node_id="56" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="396" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="401" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="406" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="411" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="1" node_id="57" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="398" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="403" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="408" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="419" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="2" node_id="58" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="400" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="417" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="420" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="415" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="3" node_id="59" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="418" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="407" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="412" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="421" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="4" node_id="60" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="416" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="399" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="404" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="409" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="5" node_id="61" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="396" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="401" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="406" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="411" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="6" node_id="62" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="398" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="403" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="408" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="419" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="7" node_id="63" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="400" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="417" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="420" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="415" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
<rr_cb x="2" y="1" num_sides="4">
|
||||
<IPIN side="top" index="0" node_id="293" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="442" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="425" index="1" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="1" node_id="294" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="422" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="427" index="3" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="2" node_id="295" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="424" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="429" index="5" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="3" node_id="296" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="426" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="443" index="7" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="4" node_id="297" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="444" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="433" index="9" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="5" node_id="298" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" node_id="430" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="435" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
<rr_cb x="2" y="2" num_sides="4">
|
||||
<IPIN side="top" index="0" node_id="388" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="468" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="451" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="456" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="461" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="1" node_id="389" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="448" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="453" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="458" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="463" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="2" node_id="390" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="450" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="455" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="460" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="471" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="3" node_id="391" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="452" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="469" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="472" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="467" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="4" node_id="392" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="470" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="459" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="464" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="473" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="5" node_id="393" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="468" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="451" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="456" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="461" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="6" node_id="394" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="448" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="453" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="458" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="463" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="7" node_id="395" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" node_id="450" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="455" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="460" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" node_id="471" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
<rr_cb x="0" y="1" num_sides="4">
|
||||
<IPIN side="right" index="0" node_id="130" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="474" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="475" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="484" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="485" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="0" node_id="88" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="476" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="477" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="486" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="487" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="1" node_id="89" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="478" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="479" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="488" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="489" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="2" node_id="90" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="480" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="481" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="490" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="491" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="3" node_id="91" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="482" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="483" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="492" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="493" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="4" node_id="92" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="474" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="475" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="484" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="485" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="5" node_id="93" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="476" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="477" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="486" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="487" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="6" node_id="94" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="478" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="479" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="488" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="489" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="7" node_id="95" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="480" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="481" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="490" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="491" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
<rr_cb x="0" y="2" num_sides="4">
|
||||
<IPIN side="right" index="0" node_id="264" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="494" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="477" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="482" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="487" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="0" node_id="222" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="474" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="479" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="484" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="489" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="1" node_id="223" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="476" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="481" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="486" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="497" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="2" node_id="224" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="478" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="495" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="498" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="493" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="3" node_id="225" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="496" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="485" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="490" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="499" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="4" node_id="226" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="494" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="477" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="482" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="487" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="5" node_id="227" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="474" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="479" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="484" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="489" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="6" node_id="228" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="476" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="481" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="486" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="497" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="7" node_id="229" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="478" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="495" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="498" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="493" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
<rr_cb x="0" y="3" num_sides="4">
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
<rr_cb x="1" y="1" num_sides="4">
|
||||
<IPIN side="right" index="0" node_id="165" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="500" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="501" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="510" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="511" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="0" node_id="118" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="502" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="503" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="512" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="513" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="1" node_id="119" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="504" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="505" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="514" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="515" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="2" node_id="120" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="506" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="507" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="516" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="517" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="3" node_id="121" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="508" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="509" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="518" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="519" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="4" node_id="122" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="500" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="501" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="510" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="511" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="5" node_id="123" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="502" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="503" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="512" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="513" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
<rr_cb x="1" y="2" num_sides="4">
|
||||
<IPIN side="right" index="0" node_id="299" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="520" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="503" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="508" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="513" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="0" node_id="252" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="500" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="505" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="510" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="515" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="1" node_id="253" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="502" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="507" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="512" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="523" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="2" node_id="254" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="504" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="521" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="524" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="519" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="3" node_id="255" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="522" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="511" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="516" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="525" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="4" node_id="256" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="520" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="503" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="508" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="513" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="5" node_id="257" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="500" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="505" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="510" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="515" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
<rr_cb x="1" y="3" num_sides="4">
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
<rr_cb x="2" y="1" num_sides="4">
|
||||
<IPIN side="right" index="0" node_id="190" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="526" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="527" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="536" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="537" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="1" node_id="191" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="528" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="529" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="538" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="539" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="2" node_id="192" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="530" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="531" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="540" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="541" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="3" node_id="193" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="532" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="533" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="542" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="543" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="4" node_id="194" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="534" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="535" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="544" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="545" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="5" node_id="195" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="526" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="527" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="536" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="537" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="6" node_id="196" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="528" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="529" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="538" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="539" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="7" node_id="197" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="530" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="531" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="540" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="541" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="0" node_id="153" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="532" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="533" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="542" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="543" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="1" node_id="154" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="534" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="535" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="544" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="545" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="2" node_id="155" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="526" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="527" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="536" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="537" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="3" node_id="156" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="528" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="529" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="538" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="539" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="4" node_id="157" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="530" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="531" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="540" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="541" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="5" node_id="158" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="532" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="533" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="542" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="543" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
<rr_cb x="2" y="2" num_sides="4">
|
||||
<IPIN side="right" index="0" node_id="324" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="546" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="529" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="534" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="539" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="1" node_id="325" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="526" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="531" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="536" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="541" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="2" node_id="326" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="528" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="533" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="538" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="549" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="3" node_id="327" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="530" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="547" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="550" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="545" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="4" node_id="328" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="548" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="537" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="542" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="551" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="5" node_id="329" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="546" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="529" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="534" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="539" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="6" node_id="330" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="526" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="531" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="536" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="541" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="7" node_id="331" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="528" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="533" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="538" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="549" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="0" node_id="287" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="530" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="547" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="550" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="545" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="1" node_id="288" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="548" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="537" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="542" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="551" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="2" node_id="289" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="546" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="529" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="534" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="539" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="3" node_id="290" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="526" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="531" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="536" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="541" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="4" node_id="291" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="528" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="533" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="538" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="549" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="5" node_id="292" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" node_id="530" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="547" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="550" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" node_id="545" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
<rr_cb x="2" y="3" num_sides="4">
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
<rr_sb x="0" y="0" num_sides="4">
|
||||
<CHANY side="top" index="0" node_id="474" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="0" node_id="80" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_0__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="right" index="3" node_id="399" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="2" node_id="476" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="1" node_id="81" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_1__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="right" index="5" node_id="401" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="4" node_id="478" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="2" node_id="82" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_2__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="right" index="7" node_id="403" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="6" node_id="480" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="3" node_id="83" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_3__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="right" index="9" node_id="405" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="8" node_id="482" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="4" node_id="84" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_4__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="right" index="11" node_id="407" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="10" node_id="484" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="5" node_id="85" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_5__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="right" index="13" node_id="409" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="12" node_id="486" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="6" node_id="86" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_6__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="right" index="15" node_id="411" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="14" node_id="488" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="7" node_id="87" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_7__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="right" index="17" node_id="413" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="16" node_id="490" segment_id="0" segment_name="L4" mux_size="1" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANX" side="right" index="19" node_id="415" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="18" node_id="492" segment_id="0" segment_name="L4" mux_size="1" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANX" side="right" index="1" node_id="397" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANY>
|
||||
<CHANX side="right" index="0" node_id="396" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="19" node_id="493" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="right" index="0" node_id="112" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_O_4_"/>
|
||||
<driver_node type="OPIN" side="right" index="10" node_id="22" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_6__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="2" node_id="398" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="1" node_id="475" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="right" index="1" node_id="113" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_O_5_"/>
|
||||
<driver_node type="OPIN" side="right" index="11" node_id="23" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_7__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="4" node_id="400" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="3" node_id="477" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="right" index="2" node_id="114" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_O_6_"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="6" node_id="402" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="5" node_id="479" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="right" index="3" node_id="115" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_O_7_"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="8" node_id="404" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="7" node_id="481" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="right" index="4" node_id="16" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_0__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="10" node_id="406" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="9" node_id="483" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="right" index="5" node_id="17" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_1__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="12" node_id="408" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="11" node_id="485" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="right" index="6" node_id="18" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_2__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="14" node_id="410" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="13" node_id="487" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="right" index="7" node_id="19" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_3__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="16" node_id="412" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="15" node_id="489" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="right" index="8" node_id="20" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_4__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="18" node_id="414" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="17" node_id="491" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="right" index="9" node_id="21" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_5__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
</rr_sb>
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
<rr_sb x="0" y="1" num_sides="4">
|
||||
<CHANY side="top" index="0" node_id="494" segment_id="0" segment_name="L4" mux_size="9" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="0" node_id="214" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_0__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="top" index="3" node_id="217" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_3__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="top" index="6" node_id="220" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_6__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="right" index="3" node_id="425" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="9" node_id="431" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="15" node_id="437" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="0" node_id="474" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="8" node_id="482" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="16" node_id="490" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="2" node_id="474" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANY" side="bottom" index="0" node_id="474" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="4" node_id="476" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANY" side="bottom" index="2" node_id="476" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="6" node_id="478" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANY" side="bottom" index="4" node_id="478" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="8" node_id="496" segment_id="0" segment_name="L4" mux_size="8" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="1" node_id="215" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_1__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="top" index="4" node_id="218" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_4__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="top" index="7" node_id="221" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_7__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="right" index="5" node_id="427" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="11" node_id="433" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="17" node_id="439" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="2" node_id="476" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="10" node_id="484" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="10" node_id="482" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANY" side="bottom" index="8" node_id="482" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="12" node_id="484" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANY" side="bottom" index="10" node_id="484" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="14" node_id="486" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANY" side="bottom" index="12" node_id="486" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="16" node_id="498" segment_id="0" segment_name="L4" mux_size="8" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="2" node_id="216" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_2__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="top" index="5" node_id="219" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_5__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="right" index="1" node_id="423" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="7" node_id="429" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="13" node_id="435" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="19" node_id="441" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="4" node_id="478" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="12" node_id="486" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="18" node_id="490" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANY" side="bottom" index="16" node_id="490" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANX side="right" index="0" node_id="422" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="1" node_id="477" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="right" index="0" node_id="246" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_O_4_"/>
|
||||
<driver_node type="CHANY" side="bottom" index="0" node_id="474" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="2" node_id="424" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="3" node_id="479" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="7" node_id="495" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="right" index="1" node_id="247" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_O_5_"/>
|
||||
<driver_node type="CHANY" side="bottom" index="2" node_id="476" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="4" node_id="426" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="5" node_id="481" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="15" node_id="497" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="right" index="2" node_id="248" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_O_6_"/>
|
||||
<driver_node type="CHANY" side="bottom" index="4" node_id="478" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="6" node_id="428" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="9" node_id="485" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="19" node_id="499" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="right" index="3" node_id="249" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_O_7_"/>
|
||||
<driver_node type="CHANY" side="bottom" index="8" node_id="482" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="8" node_id="430" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="11" node_id="487" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="10" node_id="484" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="10" node_id="432" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="13" node_id="489" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="12" node_id="486" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="12" node_id="434" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="17" node_id="493" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="16" node_id="490" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="18" node_id="492" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="14" node_id="436" segment_id="0" segment_name="L4" mux_size="1" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="bottom" index="14" node_id="488" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="16" node_id="438" segment_id="0" segment_name="L4" mux_size="1" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="bottom" index="6" node_id="480" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="18" node_id="440" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANX" side="left" index="-1" node_id="440" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANY side="bottom" index="1" node_id="475" segment_id="0" segment_name="L4" mux_size="9" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="1" node_id="477" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="9" node_id="485" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="17" node_id="493" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANX" side="right" index="3" node_id="425" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="9" node_id="431" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="15" node_id="437" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="OPIN" side="bottom" index="0" node_id="80" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_0__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="bottom" index="3" node_id="83" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_3__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="bottom" index="6" node_id="86" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_6__pin_inpad_0_"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="3" node_id="477" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="1" node_id="477" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="5" node_id="479" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="3" node_id="479" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="7" node_id="481" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="5" node_id="481" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="9" node_id="483" segment_id="0" segment_name="L4" mux_size="9" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="3" node_id="479" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="11" node_id="487" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANX" side="right" index="1" node_id="423" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="7" node_id="429" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="13" node_id="435" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="19" node_id="441" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="OPIN" side="bottom" index="1" node_id="81" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_1__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="bottom" index="4" node_id="84" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_4__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="bottom" index="7" node_id="87" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_7__pin_inpad_0_"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="11" node_id="485" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="9" node_id="485" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="13" node_id="487" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="11" node_id="487" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="15" node_id="489" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="13" node_id="489" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="17" node_id="491" segment_id="0" segment_name="L4" mux_size="7" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="5" node_id="481" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="13" node_id="489" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANX" side="right" index="5" node_id="427" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="11" node_id="433" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="17" node_id="439" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="OPIN" side="bottom" index="2" node_id="82" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_2__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="bottom" index="5" node_id="85" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_5__pin_inpad_0_"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="19" node_id="493" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="17" node_id="493" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANY>
|
||||
</rr_sb>
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
<rr_sb x="0" y="2" num_sides="4">
|
||||
<CHANX side="right" index="0" node_id="448" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="OPIN" side="right" index="0" node_id="348" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_"/>
|
||||
<driver_node type="CHANY" side="bottom" index="16" node_id="498" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="2" node_id="450" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="OPIN" side="right" index="1" node_id="349" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_"/>
|
||||
<driver_node type="CHANY" side="bottom" index="14" node_id="486" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="4" node_id="452" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="OPIN" side="right" index="2" node_id="350" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_"/>
|
||||
<driver_node type="CHANY" side="bottom" index="12" node_id="484" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="6" node_id="454" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="OPIN" side="right" index="3" node_id="351" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_"/>
|
||||
<driver_node type="CHANY" side="bottom" index="10" node_id="482" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="8" node_id="456" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="OPIN" side="right" index="4" node_id="352" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_"/>
|
||||
<driver_node type="CHANY" side="bottom" index="8" node_id="496" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="10" node_id="458" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="OPIN" side="right" index="5" node_id="353" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_"/>
|
||||
<driver_node type="CHANY" side="bottom" index="6" node_id="478" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="12" node_id="460" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="OPIN" side="right" index="6" node_id="354" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_"/>
|
||||
<driver_node type="CHANY" side="bottom" index="4" node_id="476" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="14" node_id="462" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="OPIN" side="right" index="7" node_id="355" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_"/>
|
||||
<driver_node type="CHANY" side="bottom" index="2" node_id="474" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="16" node_id="464" segment_id="0" segment_name="L4" mux_size="1" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="bottom" index="0" node_id="494" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="18" node_id="466" segment_id="0" segment_name="L4" mux_size="1" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="bottom" index="18" node_id="490" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANY side="bottom" index="1" node_id="477" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANX" side="right" index="17" node_id="465" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="OPIN" side="bottom" index="0" node_id="214" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_0__pin_inpad_0_"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="3" node_id="479" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANX" side="right" index="15" node_id="463" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="OPIN" side="bottom" index="1" node_id="215" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_1__pin_inpad_0_"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="5" node_id="481" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANX" side="right" index="13" node_id="461" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="OPIN" side="bottom" index="2" node_id="216" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_2__pin_inpad_0_"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="7" node_id="495" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANX" side="right" index="11" node_id="459" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="OPIN" side="bottom" index="3" node_id="217" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_3__pin_inpad_0_"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="9" node_id="485" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANX" side="right" index="9" node_id="457" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="OPIN" side="bottom" index="4" node_id="218" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_4__pin_inpad_0_"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="11" node_id="487" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANX" side="right" index="7" node_id="455" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="OPIN" side="bottom" index="5" node_id="219" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_5__pin_inpad_0_"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="13" node_id="489" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANX" side="right" index="5" node_id="453" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="OPIN" side="bottom" index="6" node_id="220" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_6__pin_inpad_0_"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="15" node_id="497" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANX" side="right" index="3" node_id="451" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="OPIN" side="bottom" index="7" node_id="221" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_7__pin_inpad_0_"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="17" node_id="493" segment_id="0" segment_name="L4" mux_size="1" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANX" side="right" index="1" node_id="449" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="19" node_id="499" segment_id="0" segment_name="L4" mux_size="1" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANX" side="right" index="19" node_id="467" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANY>
|
||||
</rr_sb>
|
||||
|
|
@ -0,0 +1,159 @@
|
|||
<rr_sb x="1" y="0" num_sides="4">
|
||||
<CHANY side="top" index="0" node_id="500" segment_id="0" segment_name="L4" mux_size="5" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="0" node_id="108" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_0__pin_O_0_"/>
|
||||
<driver_node type="CHANX" side="right" index="1" node_id="399" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="15" node_id="419" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="left" index="0" node_id="396" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="6" node_id="402" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="2" node_id="502" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="1" node_id="109" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_0__pin_O_1_"/>
|
||||
<driver_node type="CHANX" side="right" index="3" node_id="401" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="19" node_id="421" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="left" index="2" node_id="398" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="4" node_id="504" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="2" node_id="110" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_0__pin_O_2_"/>
|
||||
<driver_node type="CHANX" side="right" index="5" node_id="403" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="left" index="4" node_id="400" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="6" node_id="506" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="3" node_id="111" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_0__pin_O_3_"/>
|
||||
<driver_node type="CHANX" side="right" index="9" node_id="407" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="left" index="8" node_id="404" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="8" node_id="508" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANX" side="right" index="11" node_id="409" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="left" index="10" node_id="406" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="10" node_id="510" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANX" side="right" index="13" node_id="411" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="left" index="12" node_id="408" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="12" node_id="512" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANX" side="right" index="17" node_id="415" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="left" index="16" node_id="412" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="14" node_id="514" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANY" side="bottom" index="-1" node_id="514" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="16" node_id="516" segment_id="0" segment_name="L4" mux_size="1" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANX" side="left" index="18" node_id="414" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="18" node_id="518" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANX" side="right" index="7" node_id="417" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="left" index="14" node_id="410" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANX side="right" index="0" node_id="416" segment_id="0" segment_name="L4" mux_size="10" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="5" node_id="505" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="11" node_id="511" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="17" node_id="517" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="right" index="0" node_id="147" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_O_4_"/>
|
||||
<driver_node type="OPIN" side="right" index="3" node_id="150" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_O_7_"/>
|
||||
<driver_node type="OPIN" side="right" index="6" node_id="50" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_2__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="right" index="9" node_id="53" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_5__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="left" index="0" node_id="396" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="8" node_id="404" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="16" node_id="412" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="2" node_id="396" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANX" side="left" index="0" node_id="396" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="4" node_id="398" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANX" side="left" index="2" node_id="398" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="6" node_id="400" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANX" side="left" index="4" node_id="400" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="8" node_id="418" segment_id="0" segment_name="L4" mux_size="10" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="1" node_id="501" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="7" node_id="507" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="13" node_id="513" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="19" node_id="519" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="right" index="1" node_id="148" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_O_5_"/>
|
||||
<driver_node type="OPIN" side="right" index="4" node_id="48" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_0__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="right" index="7" node_id="51" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_3__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="right" index="10" node_id="54" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_6__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="left" index="2" node_id="398" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="10" node_id="406" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="10" node_id="404" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANX" side="left" index="8" node_id="404" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="12" node_id="406" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANX" side="left" index="10" node_id="406" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="14" node_id="408" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANX" side="left" index="12" node_id="408" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="16" node_id="420" segment_id="0" segment_name="L4" mux_size="9" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="3" node_id="503" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="9" node_id="509" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="15" node_id="515" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="right" index="2" node_id="149" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_O_6_"/>
|
||||
<driver_node type="OPIN" side="right" index="5" node_id="49" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_1__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="right" index="8" node_id="52" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_4__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="right" index="11" node_id="55" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_7__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="left" index="4" node_id="400" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="12" node_id="408" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="18" node_id="412" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANX" side="left" index="16" node_id="412" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="1" node_id="397" segment_id="0" segment_name="L4" mux_size="11" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="1" node_id="501" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="7" node_id="507" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="13" node_id="513" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="19" node_id="519" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANX" side="right" index="1" node_id="399" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="9" node_id="407" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="17" node_id="415" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="OPIN" side="left" index="0" node_id="112" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_O_4_"/>
|
||||
<driver_node type="OPIN" side="left" index="3" node_id="115" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_O_7_"/>
|
||||
<driver_node type="OPIN" side="left" index="6" node_id="18" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_2__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="left" index="9" node_id="21" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_5__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="3" node_id="399" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="1" node_id="399" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="5" node_id="401" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="3" node_id="401" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="7" node_id="403" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="5" node_id="403" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="9" node_id="405" segment_id="0" segment_name="L4" mux_size="9" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="5" node_id="505" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="11" node_id="511" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="17" node_id="517" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANX" side="right" index="3" node_id="401" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="11" node_id="409" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="OPIN" side="left" index="1" node_id="113" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_O_5_"/>
|
||||
<driver_node type="OPIN" side="left" index="4" node_id="16" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_0__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="left" index="7" node_id="19" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_3__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="left" index="10" node_id="22" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_6__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="11" node_id="407" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="9" node_id="407" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="13" node_id="409" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="11" node_id="409" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="15" node_id="411" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="13" node_id="411" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="17" node_id="413" segment_id="0" segment_name="L4" mux_size="9" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="3" node_id="503" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="9" node_id="509" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="15" node_id="515" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANX" side="right" index="5" node_id="403" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="13" node_id="411" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="OPIN" side="left" index="2" node_id="114" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_O_6_"/>
|
||||
<driver_node type="OPIN" side="left" index="5" node_id="17" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_1__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="left" index="8" node_id="20" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_4__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="left" index="11" node_id="23" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_7__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="19" node_id="415" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="17" node_id="415" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANX>
|
||||
</rr_sb>
|
||||
|
|
@ -0,0 +1,234 @@
|
|||
<rr_sb x="1" y="1" num_sides="4">
|
||||
<CHANY side="top" index="0" node_id="520" segment_id="0" segment_name="L4" mux_size="13" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="0" node_id="242" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_0__pin_O_0_"/>
|
||||
<driver_node type="OPIN" side="top" index="3" node_id="245" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_0__pin_O_3_"/>
|
||||
<driver_node type="CHANX" side="right" index="1" node_id="425" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="9" node_id="433" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="15" node_id="445" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="17" node_id="441" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="0" node_id="500" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="8" node_id="508" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="16" node_id="516" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANX" side="left" index="0" node_id="422" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="6" node_id="428" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="8" node_id="430" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="16" node_id="438" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="2" node_id="500" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANY" side="bottom" index="0" node_id="500" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="4" node_id="502" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANY" side="bottom" index="2" node_id="502" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="6" node_id="504" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANY" side="bottom" index="4" node_id="504" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="8" node_id="522" segment_id="0" segment_name="L4" mux_size="9" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="1" node_id="243" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_0__pin_O_1_"/>
|
||||
<driver_node type="CHANX" side="right" index="3" node_id="427" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="11" node_id="435" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="19" node_id="447" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="2" node_id="502" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="10" node_id="510" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANX" side="left" index="2" node_id="424" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="10" node_id="432" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="18" node_id="440" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="10" node_id="508" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANY" side="bottom" index="8" node_id="508" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="12" node_id="510" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANY" side="bottom" index="10" node_id="510" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="14" node_id="512" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANY" side="bottom" index="12" node_id="512" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="16" node_id="524" segment_id="0" segment_name="L4" mux_size="9" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="2" node_id="244" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_0__pin_O_2_"/>
|
||||
<driver_node type="CHANX" side="right" index="5" node_id="429" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="7" node_id="443" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="13" node_id="437" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="4" node_id="504" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="12" node_id="512" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANX" side="left" index="4" node_id="426" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="12" node_id="434" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="14" node_id="436" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="18" node_id="516" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANY" side="bottom" index="16" node_id="516" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANX side="right" index="0" node_id="442" segment_id="0" segment_name="L4" mux_size="13" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="1" node_id="503" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="9" node_id="511" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="17" node_id="519" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="19" node_id="525" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="right" index="0" node_id="281" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_O_4_"/>
|
||||
<driver_node type="OPIN" side="right" index="3" node_id="284" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_O_7_"/>
|
||||
<driver_node type="CHANY" side="bottom" index="0" node_id="500" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="8" node_id="508" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="14" node_id="514" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="16" node_id="516" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANX" side="left" index="0" node_id="422" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="8" node_id="430" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="16" node_id="438" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="2" node_id="422" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANX" side="left" index="0" node_id="422" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="4" node_id="424" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANX" side="left" index="2" node_id="424" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="6" node_id="426" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANX" side="left" index="4" node_id="426" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="8" node_id="444" segment_id="0" segment_name="L4" mux_size="9" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="3" node_id="505" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="7" node_id="521" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="11" node_id="513" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="right" index="1" node_id="282" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_O_5_"/>
|
||||
<driver_node type="CHANY" side="bottom" index="2" node_id="502" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="6" node_id="506" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="10" node_id="510" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANX" side="left" index="2" node_id="424" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="10" node_id="432" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="10" node_id="430" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANX" side="left" index="8" node_id="430" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="12" node_id="432" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANX" side="left" index="10" node_id="432" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="14" node_id="434" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANX" side="left" index="12" node_id="434" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="16" node_id="446" segment_id="0" segment_name="L4" mux_size="9" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANY" side="top" index="5" node_id="507" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="13" node_id="515" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="15" node_id="523" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="right" index="2" node_id="283" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_O_6_"/>
|
||||
<driver_node type="CHANY" side="bottom" index="4" node_id="504" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="12" node_id="512" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="18" node_id="518" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANX" side="left" index="4" node_id="426" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="12" node_id="434" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="18" node_id="438" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANX" side="left" index="16" node_id="438" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANY side="bottom" index="1" node_id="501" segment_id="0" segment_name="L4" mux_size="13" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="1" node_id="503" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="9" node_id="511" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="17" node_id="519" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANX" side="right" index="1" node_id="425" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="9" node_id="433" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="15" node_id="445" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="17" node_id="441" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="OPIN" side="bottom" index="0" node_id="108" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_0__pin_O_0_"/>
|
||||
<driver_node type="OPIN" side="bottom" index="3" node_id="111" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_0__pin_O_3_"/>
|
||||
<driver_node type="CHANX" side="left" index="0" node_id="422" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="8" node_id="430" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="14" node_id="436" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="16" node_id="438" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="3" node_id="503" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="1" node_id="503" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="5" node_id="505" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="3" node_id="505" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="7" node_id="507" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="5" node_id="507" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="9" node_id="509" segment_id="0" segment_name="L4" mux_size="9" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="3" node_id="505" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="11" node_id="513" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANX" side="right" index="3" node_id="427" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="7" node_id="443" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="11" node_id="435" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="OPIN" side="bottom" index="1" node_id="109" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_0__pin_O_1_"/>
|
||||
<driver_node type="CHANX" side="left" index="2" node_id="424" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="10" node_id="432" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="18" node_id="440" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="11" node_id="511" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="9" node_id="511" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="13" node_id="513" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="11" node_id="513" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="15" node_id="515" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="13" node_id="515" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="17" node_id="517" segment_id="0" segment_name="L4" mux_size="9" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="5" node_id="507" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="13" node_id="515" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANX" side="right" index="5" node_id="429" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="13" node_id="437" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="19" node_id="447" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="OPIN" side="bottom" index="2" node_id="110" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_0__pin_O_2_"/>
|
||||
<driver_node type="CHANX" side="left" index="4" node_id="426" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="6" node_id="428" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="12" node_id="434" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="19" node_id="519" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="17" node_id="519" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANY>
|
||||
<CHANX side="left" index="1" node_id="423" segment_id="0" segment_name="L4" mux_size="13" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="1" node_id="503" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="7" node_id="521" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="9" node_id="511" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="17" node_id="519" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANX" side="right" index="1" node_id="425" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="9" node_id="433" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="17" node_id="441" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="0" node_id="500" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="8" node_id="508" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="16" node_id="516" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="18" node_id="518" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="OPIN" side="left" index="0" node_id="246" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_O_4_"/>
|
||||
<driver_node type="OPIN" side="left" index="3" node_id="249" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_O_7_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="3" node_id="425" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="1" node_id="425" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="5" node_id="427" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="3" node_id="427" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="7" node_id="429" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="5" node_id="429" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="9" node_id="431" segment_id="0" segment_name="L4" mux_size="9" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="3" node_id="505" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="11" node_id="513" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="19" node_id="525" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANX" side="right" index="3" node_id="427" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="11" node_id="435" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="2" node_id="502" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="6" node_id="506" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="10" node_id="510" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="OPIN" side="left" index="1" node_id="247" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_O_5_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="11" node_id="433" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="9" node_id="433" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="13" node_id="435" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="11" node_id="435" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="15" node_id="437" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="13" node_id="437" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="17" node_id="439" segment_id="0" segment_name="L4" mux_size="9" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="5" node_id="507" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="13" node_id="515" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="15" node_id="523" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANX" side="right" index="5" node_id="429" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="13" node_id="437" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="4" node_id="504" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="12" node_id="512" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="14" node_id="514" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="OPIN" side="left" index="2" node_id="248" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_O_6_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="19" node_id="441" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="17" node_id="441" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANX>
|
||||
</rr_sb>
|
||||
|
|
@ -0,0 +1,150 @@
|
|||
<rr_sb x="1" y="2" num_sides="4">
|
||||
<CHANX side="right" index="0" node_id="468" segment_id="0" segment_name="L4" mux_size="9" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="OPIN" side="right" index="0" node_id="380" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="right" index="3" node_id="383" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="right" index="6" node_id="386" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_"/>
|
||||
<driver_node type="CHANY" side="bottom" index="2" node_id="500" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="8" node_id="522" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="14" node_id="512" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANX" side="left" index="0" node_id="448" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="8" node_id="456" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="16" node_id="464" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="2" node_id="448" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANX" side="left" index="0" node_id="448" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="4" node_id="450" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANX" side="left" index="2" node_id="450" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="6" node_id="452" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANX" side="left" index="4" node_id="452" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="8" node_id="470" segment_id="0" segment_name="L4" mux_size="9" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="OPIN" side="right" index="1" node_id="381" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="right" index="4" node_id="384" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="right" index="7" node_id="387" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_"/>
|
||||
<driver_node type="CHANY" side="bottom" index="0" node_id="520" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="6" node_id="504" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="12" node_id="510" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="18" node_id="516" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANX" side="left" index="2" node_id="450" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="10" node_id="458" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="10" node_id="456" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANX" side="left" index="8" node_id="456" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="12" node_id="458" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANX" side="left" index="10" node_id="458" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="14" node_id="460" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANX" side="left" index="12" node_id="460" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="16" node_id="472" segment_id="0" segment_name="L4" mux_size="7" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="OPIN" side="right" index="2" node_id="382" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="right" index="5" node_id="385" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_"/>
|
||||
<driver_node type="CHANY" side="bottom" index="4" node_id="502" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="10" node_id="508" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="16" node_id="524" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANX" side="left" index="4" node_id="452" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="12" node_id="460" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="18" node_id="464" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_right_out">
|
||||
<driver_node type="CHANX" side="left" index="16" node_id="464" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANX>
|
||||
<CHANY side="bottom" index="1" node_id="503" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANX" side="right" index="1" node_id="451" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="OPIN" side="bottom" index="0" node_id="242" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_0__pin_O_0_"/>
|
||||
<driver_node type="CHANX" side="left" index="0" node_id="448" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="14" node_id="462" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="3" node_id="505" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANX" side="right" index="3" node_id="453" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="OPIN" side="bottom" index="1" node_id="243" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_0__pin_O_1_"/>
|
||||
<driver_node type="CHANX" side="left" index="2" node_id="450" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="18" node_id="466" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="5" node_id="507" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANX" side="right" index="5" node_id="455" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="OPIN" side="bottom" index="2" node_id="244" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_0__pin_O_2_"/>
|
||||
<driver_node type="CHANX" side="left" index="4" node_id="452" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="7" node_id="521" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANX" side="right" index="9" node_id="459" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="OPIN" side="bottom" index="3" node_id="245" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_0__pin_O_3_"/>
|
||||
<driver_node type="CHANX" side="left" index="8" node_id="456" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="9" node_id="511" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANX" side="right" index="11" node_id="461" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="left" index="10" node_id="458" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="11" node_id="513" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANX" side="right" index="13" node_id="463" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="left" index="12" node_id="460" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="13" node_id="515" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANX" side="right" index="17" node_id="467" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="19" node_id="473" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="left" index="16" node_id="464" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="15" node_id="523" segment_id="0" segment_name="L4" mux_size="1" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANX" side="right" index="15" node_id="471" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="17" node_id="519" segment_id="0" segment_name="L4" mux_size="1" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANX" side="right" index="7" node_id="469" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="19" node_id="525" segment_id="0" segment_name="L4" mux_size="1" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANX" side="left" index="6" node_id="454" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANX side="left" index="1" node_id="449" segment_id="0" segment_name="L4" mux_size="9" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="1" node_id="451" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="9" node_id="459" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="17" node_id="467" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="4" node_id="502" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="10" node_id="508" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="16" node_id="524" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="OPIN" side="left" index="0" node_id="348" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="left" index="3" node_id="351" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="left" index="6" node_id="354" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="3" node_id="451" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="1" node_id="451" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="5" node_id="453" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="3" node_id="453" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="7" node_id="455" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="5" node_id="455" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="9" node_id="457" segment_id="0" segment_name="L4" mux_size="9" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="3" node_id="453" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="11" node_id="461" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="0" node_id="520" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="6" node_id="504" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="12" node_id="510" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="18" node_id="516" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="OPIN" side="left" index="1" node_id="349" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="left" index="4" node_id="352" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="left" index="7" node_id="355" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="11" node_id="459" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="9" node_id="459" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="13" node_id="461" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="11" node_id="461" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="15" node_id="463" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="13" node_id="463" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="17" node_id="465" segment_id="0" segment_name="L4" mux_size="7" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="5" node_id="455" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANX" side="right" index="13" node_id="463" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="2" node_id="500" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="8" node_id="522" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="14" node_id="512" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="OPIN" side="left" index="2" node_id="350" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="left" index="5" node_id="353" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="19" node_id="467" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="17" node_id="467" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANX>
|
||||
</rr_sb>
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
<rr_sb x="2" y="0" num_sides="4">
|
||||
<CHANY side="top" index="0" node_id="526" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="0" node_id="143" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_0__pin_O_0_"/>
|
||||
<driver_node type="OPIN" side="top" index="10" node_id="188" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_6__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="left" index="0" node_id="416" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="2" node_id="528" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="1" node_id="144" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_0__pin_O_1_"/>
|
||||
<driver_node type="OPIN" side="top" index="11" node_id="189" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_7__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="left" index="18" node_id="412" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="4" node_id="530" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="2" node_id="145" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_0__pin_O_2_"/>
|
||||
<driver_node type="CHANX" side="left" index="16" node_id="420" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="6" node_id="532" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="3" node_id="146" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_0__pin_O_3_"/>
|
||||
<driver_node type="CHANX" side="left" index="14" node_id="408" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="8" node_id="534" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="4" node_id="182" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_0__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="left" index="12" node_id="406" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="10" node_id="536" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="5" node_id="183" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_1__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="left" index="10" node_id="404" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="12" node_id="538" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="6" node_id="184" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_2__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="left" index="8" node_id="418" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="14" node_id="540" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="7" node_id="185" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_3__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="left" index="6" node_id="400" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="16" node_id="542" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="8" node_id="186" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_4__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="left" index="4" node_id="398" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="18" node_id="544" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="9" node_id="187" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_5__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="left" index="2" node_id="396" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANX side="left" index="1" node_id="399" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="1" node_id="527" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="left" index="0" node_id="147" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_O_4_"/>
|
||||
<driver_node type="OPIN" side="left" index="10" node_id="54" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_6__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="3" node_id="401" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="19" node_id="545" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="left" index="1" node_id="148" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_O_5_"/>
|
||||
<driver_node type="OPIN" side="left" index="11" node_id="55" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_7__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="5" node_id="403" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="17" node_id="543" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="left" index="2" node_id="149" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_O_6_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="7" node_id="417" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="15" node_id="541" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="left" index="3" node_id="150" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_O_7_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="9" node_id="407" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="13" node_id="539" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="left" index="4" node_id="48" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_0__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="11" node_id="409" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="11" node_id="537" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="left" index="5" node_id="49" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_1__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="13" node_id="411" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="9" node_id="535" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="left" index="6" node_id="50" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_2__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="15" node_id="419" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="7" node_id="533" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="left" index="7" node_id="51" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_3__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="17" node_id="415" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="5" node_id="531" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="left" index="8" node_id="52" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_4__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="19" node_id="421" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="3" node_id="529" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="left" index="9" node_id="53" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_5__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
</rr_sb>
|
||||
|
|
@ -0,0 +1,159 @@
|
|||
<rr_sb x="2" y="1" num_sides="4">
|
||||
<CHANY side="top" index="0" node_id="546" segment_id="0" segment_name="L4" mux_size="11" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="0" node_id="277" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_0__pin_O_0_"/>
|
||||
<driver_node type="OPIN" side="top" index="3" node_id="280" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_0__pin_O_3_"/>
|
||||
<driver_node type="OPIN" side="top" index="6" node_id="318" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_2__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="top" index="9" node_id="321" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_5__pin_inpad_0_"/>
|
||||
<driver_node type="CHANY" side="bottom" index="0" node_id="526" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="8" node_id="534" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="16" node_id="542" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANX" side="left" index="0" node_id="442" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="6" node_id="426" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="12" node_id="432" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="18" node_id="438" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="2" node_id="526" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANY" side="bottom" index="0" node_id="526" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="4" node_id="528" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANY" side="bottom" index="2" node_id="528" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="6" node_id="530" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANY" side="bottom" index="4" node_id="530" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="8" node_id="548" segment_id="0" segment_name="L4" mux_size="9" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="1" node_id="278" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_0__pin_O_1_"/>
|
||||
<driver_node type="OPIN" side="top" index="4" node_id="316" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_0__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="top" index="7" node_id="319" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_3__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="top" index="10" node_id="322" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_6__pin_inpad_0_"/>
|
||||
<driver_node type="CHANY" side="bottom" index="2" node_id="528" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="10" node_id="536" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANX" side="left" index="4" node_id="424" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="10" node_id="430" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="16" node_id="446" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="10" node_id="534" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANY" side="bottom" index="8" node_id="534" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="12" node_id="536" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANY" side="bottom" index="10" node_id="536" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="14" node_id="538" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANY" side="bottom" index="12" node_id="538" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="16" node_id="550" segment_id="0" segment_name="L4" mux_size="9" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="OPIN" side="top" index="2" node_id="279" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_0__pin_O_2_"/>
|
||||
<driver_node type="OPIN" side="top" index="5" node_id="317" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_1__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="top" index="8" node_id="320" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_4__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="top" index="11" node_id="323" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_7__pin_inpad_0_"/>
|
||||
<driver_node type="CHANY" side="bottom" index="4" node_id="530" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="12" node_id="538" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANX" side="left" index="2" node_id="422" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="8" node_id="444" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="14" node_id="434" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="18" node_id="542" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_top_out">
|
||||
<driver_node type="CHANY" side="bottom" index="16" node_id="542" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="1" node_id="527" segment_id="0" segment_name="L4" mux_size="10" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="1" node_id="529" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="9" node_id="537" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="17" node_id="545" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="bottom" index="0" node_id="182" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_0__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="bottom" index="3" node_id="185" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_3__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="bottom" index="6" node_id="188" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_6__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="bottom" index="9" node_id="144" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_0__pin_O_1_"/>
|
||||
<driver_node type="CHANX" side="left" index="2" node_id="422" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="8" node_id="444" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="14" node_id="434" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="3" node_id="529" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="1" node_id="529" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="5" node_id="531" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="3" node_id="531" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="7" node_id="533" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="5" node_id="533" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="9" node_id="535" segment_id="0" segment_name="L4" mux_size="9" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="3" node_id="531" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="11" node_id="539" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="bottom" index="1" node_id="183" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_1__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="bottom" index="4" node_id="186" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_4__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="bottom" index="7" node_id="189" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_7__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="bottom" index="10" node_id="145" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_0__pin_O_2_"/>
|
||||
<driver_node type="CHANX" side="left" index="4" node_id="424" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="10" node_id="430" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="16" node_id="446" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="11" node_id="537" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="9" node_id="537" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="13" node_id="539" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="11" node_id="539" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="15" node_id="541" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="13" node_id="541" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="17" node_id="543" segment_id="0" segment_name="L4" mux_size="10" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="5" node_id="533" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="13" node_id="541" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="OPIN" side="bottom" index="2" node_id="184" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_2__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="bottom" index="5" node_id="187" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_5__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="bottom" index="8" node_id="143" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_0__pin_O_0_"/>
|
||||
<driver_node type="OPIN" side="bottom" index="11" node_id="146" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_0__pin_O_3_"/>
|
||||
<driver_node type="CHANX" side="left" index="0" node_id="442" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="6" node_id="426" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="12" node_id="432" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
<driver_node type="CHANX" side="left" index="18" node_id="438" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="19" node_id="545" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="CHANY" side="top" index="17" node_id="545" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANY>
|
||||
<CHANX side="left" index="1" node_id="425" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="1" node_id="529" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="top" index="7" node_id="547" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="0" node_id="526" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="OPIN" side="left" index="0" node_id="281" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_O_4_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="3" node_id="427" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="3" node_id="531" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="2" node_id="528" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="6" node_id="532" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="OPIN" side="left" index="1" node_id="282" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_O_5_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="5" node_id="429" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="5" node_id="533" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="4" node_id="530" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="14" node_id="540" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="OPIN" side="left" index="2" node_id="283" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_O_6_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="7" node_id="443" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="9" node_id="537" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="8" node_id="534" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="18" node_id="544" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="OPIN" side="left" index="3" node_id="284" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_O_7_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="9" node_id="433" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="11" node_id="539" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="10" node_id="536" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="11" node_id="435" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="13" node_id="541" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="12" node_id="538" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="13" node_id="437" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="17" node_id="545" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
<driver_node type="CHANY" side="bottom" index="16" node_id="542" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="15" node_id="445" segment_id="0" segment_name="L4" mux_size="0" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANX" side="right" index="-1" node_id="445" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="17" node_id="441" segment_id="0" segment_name="L4" mux_size="1" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="19" node_id="551" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="19" node_id="447" segment_id="0" segment_name="L4" mux_size="1" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="top" index="15" node_id="549" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
|
||||
</CHANX>
|
||||
</rr_sb>
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
<rr_sb x="2" y="2" num_sides="4">
|
||||
<CHANY side="bottom" index="1" node_id="529" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="OPIN" side="bottom" index="0" node_id="316" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_0__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="bottom" index="10" node_id="279" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_0__pin_O_2_"/>
|
||||
<driver_node type="CHANX" side="left" index="2" node_id="448" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="3" node_id="531" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="OPIN" side="bottom" index="1" node_id="317" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_1__pin_inpad_0_"/>
|
||||
<driver_node type="OPIN" side="bottom" index="11" node_id="280" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_0__pin_O_3_"/>
|
||||
<driver_node type="CHANX" side="left" index="4" node_id="450" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="5" node_id="533" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="OPIN" side="bottom" index="2" node_id="318" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_2__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="left" index="6" node_id="452" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="7" node_id="547" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="OPIN" side="bottom" index="3" node_id="319" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_3__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="left" index="8" node_id="470" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="9" node_id="537" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="OPIN" side="bottom" index="4" node_id="320" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_4__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="left" index="10" node_id="456" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="11" node_id="539" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="OPIN" side="bottom" index="5" node_id="321" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_5__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="left" index="12" node_id="458" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="13" node_id="541" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="OPIN" side="bottom" index="6" node_id="322" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_6__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="left" index="14" node_id="460" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="15" node_id="549" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="OPIN" side="bottom" index="7" node_id="323" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_7__pin_inpad_0_"/>
|
||||
<driver_node type="CHANX" side="left" index="16" node_id="472" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="17" node_id="545" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="OPIN" side="bottom" index="8" node_id="277" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_0__pin_O_0_"/>
|
||||
<driver_node type="CHANX" side="left" index="18" node_id="464" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="19" node_id="551" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
|
||||
<driver_node type="OPIN" side="bottom" index="9" node_id="278" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_0__pin_O_1_"/>
|
||||
<driver_node type="CHANX" side="left" index="0" node_id="468" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
|
||||
</CHANY>
|
||||
<CHANX side="left" index="1" node_id="451" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="bottom" index="18" node_id="542" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="OPIN" side="left" index="0" node_id="380" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="3" node_id="453" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="bottom" index="0" node_id="546" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="OPIN" side="left" index="1" node_id="381" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="5" node_id="455" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="bottom" index="2" node_id="526" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="OPIN" side="left" index="2" node_id="382" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="7" node_id="469" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="bottom" index="4" node_id="528" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="OPIN" side="left" index="3" node_id="383" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="9" node_id="459" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="bottom" index="6" node_id="530" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="OPIN" side="left" index="4" node_id="384" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="11" node_id="461" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="bottom" index="8" node_id="548" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="OPIN" side="left" index="5" node_id="385" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="13" node_id="463" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="bottom" index="10" node_id="534" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="OPIN" side="left" index="6" node_id="386" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="15" node_id="471" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="bottom" index="12" node_id="536" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
<driver_node type="OPIN" side="left" index="7" node_id="387" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="17" node_id="467" segment_id="0" segment_name="L4" mux_size="1" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="bottom" index="14" node_id="538" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="19" node_id="473" segment_id="0" segment_name="L4" mux_size="1" sb_module_pin_name="chanx_left_out">
|
||||
<driver_node type="CHANY" side="bottom" index="16" node_id="550" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
|
||||
</CHANX>
|
||||
</rr_sb>
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
<rr_cb x="0" y="0" num_sides="4">
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
<rr_cb x="0" y="1" num_sides="4">
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
<rr_cb x="0" y="2" num_sides="4">
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
<rr_cb x="1" y="0" num_sides="4">
|
||||
<IPIN side="top" index="0" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="1" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="1" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="3" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="2" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="5" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="3" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="7" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="4" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="9" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="5" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="0" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="1" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="2" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="3" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="4" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="5" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="6" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="7" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
<rr_cb x="1" y="1" num_sides="4">
|
||||
<IPIN side="top" index="0" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="1" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="1" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="3" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="2" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="5" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="3" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="7" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="4" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="9" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="5" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
<rr_cb x="1" y="2" num_sides="4">
|
||||
<IPIN side="top" index="0" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="1" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="2" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="3" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="4" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="5" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="6" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="7" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
<rr_cb x="2" y="0" num_sides="4">
|
||||
<IPIN side="top" index="0" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="1" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="1" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="3" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="2" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="5" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="3" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="7" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="4" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="9" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="5" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="0" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="1" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="2" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="3" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="4" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="5" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="6" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="bottom" index="7" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
<rr_cb x="2" y="1" num_sides="4">
|
||||
<IPIN side="top" index="0" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="1" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="1" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="3" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="2" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="5" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="3" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="7" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="4" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="9" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="5" mux_size="2">
|
||||
<driver_node type="CHANX" side="left" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
<rr_cb x="2" y="2" num_sides="4">
|
||||
<IPIN side="top" index="0" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="1" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="2" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="3" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="4" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="5" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="6" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="top" index="7" mux_size="4">
|
||||
<driver_node type="CHANX" side="left" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANX" side="left" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
<rr_cb x="0" y="1" num_sides="4">
|
||||
<IPIN side="right" index="0" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="0" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="1" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="2" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="3" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="4" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="5" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="6" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="7" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
<rr_cb x="0" y="2" num_sides="4">
|
||||
<IPIN side="right" index="0" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="0" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="1" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="2" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="3" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="4" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="5" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="6" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="7" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
<rr_cb x="0" y="3" num_sides="4">
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
<rr_cb x="1" y="1" num_sides="4">
|
||||
<IPIN side="right" index="0" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="0" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="1" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="2" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="3" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="4" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="5" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
<rr_cb x="1" y="2" num_sides="4">
|
||||
<IPIN side="right" index="0" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="0" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="1" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="2" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="3" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="4" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="5" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
<rr_cb x="1" y="3" num_sides="4">
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
<rr_cb x="2" y="1" num_sides="4">
|
||||
<IPIN side="right" index="0" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="1" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="2" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="3" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="4" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="5" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="6" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="7" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="0" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="1" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="2" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="3" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="4" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="5" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
<rr_cb x="2" y="2" num_sides="4">
|
||||
<IPIN side="right" index="0" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="1" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="2" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="3" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="4" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="5" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="6" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="right" index="7" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="0" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="1" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="2" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="3" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="4" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
|
||||
</IPIN>
|
||||
<IPIN side="left" index="5" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
|
||||
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
|
||||
</IPIN>
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
<rr_cb x="2" y="3" num_sides="4">
|
||||
</rr_cb>
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
<rr_sb x="0" y="0" num_sides="4">
|
||||
<CHANY side="top" index="0" mux_size="2">
|
||||
<driver_node type="OPIN" side="top" index="0"/>
|
||||
<driver_node type="CHANX" side="right" index="3"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="2" mux_size="2">
|
||||
<driver_node type="OPIN" side="top" index="1"/>
|
||||
<driver_node type="CHANX" side="right" index="5"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="4" mux_size="2">
|
||||
<driver_node type="OPIN" side="top" index="2"/>
|
||||
<driver_node type="CHANX" side="right" index="7"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="6" mux_size="2">
|
||||
<driver_node type="OPIN" side="top" index="3"/>
|
||||
<driver_node type="CHANX" side="right" index="9"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="8" mux_size="2">
|
||||
<driver_node type="OPIN" side="top" index="4"/>
|
||||
<driver_node type="CHANX" side="right" index="11"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="10" mux_size="2">
|
||||
<driver_node type="OPIN" side="top" index="5"/>
|
||||
<driver_node type="CHANX" side="right" index="13"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="12" mux_size="2">
|
||||
<driver_node type="OPIN" side="top" index="6"/>
|
||||
<driver_node type="CHANX" side="right" index="15"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="14" mux_size="2">
|
||||
<driver_node type="OPIN" side="top" index="7"/>
|
||||
<driver_node type="CHANX" side="right" index="17"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="16" mux_size="1">
|
||||
<driver_node type="CHANX" side="right" index="19"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="18" mux_size="1">
|
||||
<driver_node type="CHANX" side="right" index="1"/>
|
||||
</CHANY>
|
||||
<CHANX side="right" index="0" mux_size="3">
|
||||
<driver_node type="CHANY" side="top" index="19"/>
|
||||
<driver_node type="OPIN" side="right" index="0"/>
|
||||
<driver_node type="OPIN" side="right" index="10"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="2" mux_size="3">
|
||||
<driver_node type="CHANY" side="top" index="1"/>
|
||||
<driver_node type="OPIN" side="right" index="1"/>
|
||||
<driver_node type="OPIN" side="right" index="11"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="4" mux_size="2">
|
||||
<driver_node type="CHANY" side="top" index="3"/>
|
||||
<driver_node type="OPIN" side="right" index="2"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="6" mux_size="2">
|
||||
<driver_node type="CHANY" side="top" index="5"/>
|
||||
<driver_node type="OPIN" side="right" index="3"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="8" mux_size="2">
|
||||
<driver_node type="CHANY" side="top" index="7"/>
|
||||
<driver_node type="OPIN" side="right" index="4"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="10" mux_size="2">
|
||||
<driver_node type="CHANY" side="top" index="9"/>
|
||||
<driver_node type="OPIN" side="right" index="5"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="12" mux_size="2">
|
||||
<driver_node type="CHANY" side="top" index="11"/>
|
||||
<driver_node type="OPIN" side="right" index="6"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="14" mux_size="2">
|
||||
<driver_node type="CHANY" side="top" index="13"/>
|
||||
<driver_node type="OPIN" side="right" index="7"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="16" mux_size="2">
|
||||
<driver_node type="CHANY" side="top" index="15"/>
|
||||
<driver_node type="OPIN" side="right" index="8"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="18" mux_size="2">
|
||||
<driver_node type="CHANY" side="top" index="17"/>
|
||||
<driver_node type="OPIN" side="right" index="9"/>
|
||||
</CHANX>
|
||||
</rr_sb>
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
<rr_sb x="0" y="1" num_sides="4">
|
||||
<CHANY side="top" index="0" mux_size="9">
|
||||
<driver_node type="OPIN" side="top" index="0"/>
|
||||
<driver_node type="OPIN" side="top" index="3"/>
|
||||
<driver_node type="OPIN" side="top" index="6"/>
|
||||
<driver_node type="CHANX" side="right" index="3"/>
|
||||
<driver_node type="CHANX" side="right" index="9"/>
|
||||
<driver_node type="CHANX" side="right" index="15"/>
|
||||
<driver_node type="CHANY" side="bottom" index="0"/>
|
||||
<driver_node type="CHANY" side="bottom" index="8"/>
|
||||
<driver_node type="CHANY" side="bottom" index="16"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="2" mux_size="0">
|
||||
<driver_node type="CHANY" side="bottom" index="0"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="4" mux_size="0">
|
||||
<driver_node type="CHANY" side="bottom" index="2"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="6" mux_size="0">
|
||||
<driver_node type="CHANY" side="bottom" index="4"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="8" mux_size="8">
|
||||
<driver_node type="OPIN" side="top" index="1"/>
|
||||
<driver_node type="OPIN" side="top" index="4"/>
|
||||
<driver_node type="OPIN" side="top" index="7"/>
|
||||
<driver_node type="CHANX" side="right" index="5"/>
|
||||
<driver_node type="CHANX" side="right" index="11"/>
|
||||
<driver_node type="CHANX" side="right" index="17"/>
|
||||
<driver_node type="CHANY" side="bottom" index="2"/>
|
||||
<driver_node type="CHANY" side="bottom" index="10"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="10" mux_size="0">
|
||||
<driver_node type="CHANY" side="bottom" index="8"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="12" mux_size="0">
|
||||
<driver_node type="CHANY" side="bottom" index="10"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="14" mux_size="0">
|
||||
<driver_node type="CHANY" side="bottom" index="12"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="16" mux_size="8">
|
||||
<driver_node type="OPIN" side="top" index="2"/>
|
||||
<driver_node type="OPIN" side="top" index="5"/>
|
||||
<driver_node type="CHANX" side="right" index="1"/>
|
||||
<driver_node type="CHANX" side="right" index="7"/>
|
||||
<driver_node type="CHANX" side="right" index="13"/>
|
||||
<driver_node type="CHANX" side="right" index="19"/>
|
||||
<driver_node type="CHANY" side="bottom" index="4"/>
|
||||
<driver_node type="CHANY" side="bottom" index="12"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="18" mux_size="0">
|
||||
<driver_node type="CHANY" side="bottom" index="16"/>
|
||||
</CHANY>
|
||||
<CHANX side="right" index="0" mux_size="3">
|
||||
<driver_node type="CHANY" side="top" index="1"/>
|
||||
<driver_node type="OPIN" side="right" index="0"/>
|
||||
<driver_node type="CHANY" side="bottom" index="0"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="2" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="3"/>
|
||||
<driver_node type="CHANY" side="top" index="7"/>
|
||||
<driver_node type="OPIN" side="right" index="1"/>
|
||||
<driver_node type="CHANY" side="bottom" index="2"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="4" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="5"/>
|
||||
<driver_node type="CHANY" side="top" index="15"/>
|
||||
<driver_node type="OPIN" side="right" index="2"/>
|
||||
<driver_node type="CHANY" side="bottom" index="4"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="6" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="9"/>
|
||||
<driver_node type="CHANY" side="top" index="19"/>
|
||||
<driver_node type="OPIN" side="right" index="3"/>
|
||||
<driver_node type="CHANY" side="bottom" index="8"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="8" mux_size="2">
|
||||
<driver_node type="CHANY" side="top" index="11"/>
|
||||
<driver_node type="CHANY" side="bottom" index="10"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="10" mux_size="2">
|
||||
<driver_node type="CHANY" side="top" index="13"/>
|
||||
<driver_node type="CHANY" side="bottom" index="12"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="12" mux_size="3">
|
||||
<driver_node type="CHANY" side="top" index="17"/>
|
||||
<driver_node type="CHANY" side="bottom" index="16"/>
|
||||
<driver_node type="CHANY" side="bottom" index="18"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="14" mux_size="1">
|
||||
<driver_node type="CHANY" side="bottom" index="14"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="16" mux_size="1">
|
||||
<driver_node type="CHANY" side="bottom" index="6"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="18" mux_size="0">
|
||||
<driver_node type="CHANX" side="left" index="-1"/>
|
||||
</CHANX>
|
||||
<CHANY side="bottom" index="1" mux_size="9">
|
||||
<driver_node type="CHANY" side="top" index="1"/>
|
||||
<driver_node type="CHANY" side="top" index="9"/>
|
||||
<driver_node type="CHANY" side="top" index="17"/>
|
||||
<driver_node type="CHANX" side="right" index="3"/>
|
||||
<driver_node type="CHANX" side="right" index="9"/>
|
||||
<driver_node type="CHANX" side="right" index="15"/>
|
||||
<driver_node type="OPIN" side="bottom" index="0"/>
|
||||
<driver_node type="OPIN" side="bottom" index="3"/>
|
||||
<driver_node type="OPIN" side="bottom" index="6"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="3" mux_size="0">
|
||||
<driver_node type="CHANY" side="top" index="1"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="5" mux_size="0">
|
||||
<driver_node type="CHANY" side="top" index="3"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="7" mux_size="0">
|
||||
<driver_node type="CHANY" side="top" index="5"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="9" mux_size="9">
|
||||
<driver_node type="CHANY" side="top" index="3"/>
|
||||
<driver_node type="CHANY" side="top" index="11"/>
|
||||
<driver_node type="CHANX" side="right" index="1"/>
|
||||
<driver_node type="CHANX" side="right" index="7"/>
|
||||
<driver_node type="CHANX" side="right" index="13"/>
|
||||
<driver_node type="CHANX" side="right" index="19"/>
|
||||
<driver_node type="OPIN" side="bottom" index="1"/>
|
||||
<driver_node type="OPIN" side="bottom" index="4"/>
|
||||
<driver_node type="OPIN" side="bottom" index="7"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="11" mux_size="0">
|
||||
<driver_node type="CHANY" side="top" index="9"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="13" mux_size="0">
|
||||
<driver_node type="CHANY" side="top" index="11"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="15" mux_size="0">
|
||||
<driver_node type="CHANY" side="top" index="13"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="17" mux_size="7">
|
||||
<driver_node type="CHANY" side="top" index="5"/>
|
||||
<driver_node type="CHANY" side="top" index="13"/>
|
||||
<driver_node type="CHANX" side="right" index="5"/>
|
||||
<driver_node type="CHANX" side="right" index="11"/>
|
||||
<driver_node type="CHANX" side="right" index="17"/>
|
||||
<driver_node type="OPIN" side="bottom" index="2"/>
|
||||
<driver_node type="OPIN" side="bottom" index="5"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="19" mux_size="0">
|
||||
<driver_node type="CHANY" side="top" index="17"/>
|
||||
</CHANY>
|
||||
</rr_sb>
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
<rr_sb x="0" y="2" num_sides="4">
|
||||
<CHANX side="right" index="0" mux_size="2">
|
||||
<driver_node type="OPIN" side="right" index="0"/>
|
||||
<driver_node type="CHANY" side="bottom" index="16"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="2" mux_size="2">
|
||||
<driver_node type="OPIN" side="right" index="1"/>
|
||||
<driver_node type="CHANY" side="bottom" index="14"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="4" mux_size="2">
|
||||
<driver_node type="OPIN" side="right" index="2"/>
|
||||
<driver_node type="CHANY" side="bottom" index="12"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="6" mux_size="2">
|
||||
<driver_node type="OPIN" side="right" index="3"/>
|
||||
<driver_node type="CHANY" side="bottom" index="10"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="8" mux_size="2">
|
||||
<driver_node type="OPIN" side="right" index="4"/>
|
||||
<driver_node type="CHANY" side="bottom" index="8"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="10" mux_size="2">
|
||||
<driver_node type="OPIN" side="right" index="5"/>
|
||||
<driver_node type="CHANY" side="bottom" index="6"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="12" mux_size="2">
|
||||
<driver_node type="OPIN" side="right" index="6"/>
|
||||
<driver_node type="CHANY" side="bottom" index="4"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="14" mux_size="2">
|
||||
<driver_node type="OPIN" side="right" index="7"/>
|
||||
<driver_node type="CHANY" side="bottom" index="2"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="16" mux_size="1">
|
||||
<driver_node type="CHANY" side="bottom" index="0"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="18" mux_size="1">
|
||||
<driver_node type="CHANY" side="bottom" index="18"/>
|
||||
</CHANX>
|
||||
<CHANY side="bottom" index="1" mux_size="2">
|
||||
<driver_node type="CHANX" side="right" index="17"/>
|
||||
<driver_node type="OPIN" side="bottom" index="0"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="3" mux_size="2">
|
||||
<driver_node type="CHANX" side="right" index="15"/>
|
||||
<driver_node type="OPIN" side="bottom" index="1"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="5" mux_size="2">
|
||||
<driver_node type="CHANX" side="right" index="13"/>
|
||||
<driver_node type="OPIN" side="bottom" index="2"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="7" mux_size="2">
|
||||
<driver_node type="CHANX" side="right" index="11"/>
|
||||
<driver_node type="OPIN" side="bottom" index="3"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="9" mux_size="2">
|
||||
<driver_node type="CHANX" side="right" index="9"/>
|
||||
<driver_node type="OPIN" side="bottom" index="4"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="11" mux_size="2">
|
||||
<driver_node type="CHANX" side="right" index="7"/>
|
||||
<driver_node type="OPIN" side="bottom" index="5"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="13" mux_size="2">
|
||||
<driver_node type="CHANX" side="right" index="5"/>
|
||||
<driver_node type="OPIN" side="bottom" index="6"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="15" mux_size="2">
|
||||
<driver_node type="CHANX" side="right" index="3"/>
|
||||
<driver_node type="OPIN" side="bottom" index="7"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="17" mux_size="1">
|
||||
<driver_node type="CHANX" side="right" index="1"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="19" mux_size="1">
|
||||
<driver_node type="CHANX" side="right" index="19"/>
|
||||
</CHANY>
|
||||
</rr_sb>
|
||||
|
|
@ -0,0 +1,159 @@
|
|||
<rr_sb x="1" y="0" num_sides="4">
|
||||
<CHANY side="top" index="0" mux_size="5">
|
||||
<driver_node type="OPIN" side="top" index="0"/>
|
||||
<driver_node type="CHANX" side="right" index="1"/>
|
||||
<driver_node type="CHANX" side="right" index="15"/>
|
||||
<driver_node type="CHANX" side="left" index="0"/>
|
||||
<driver_node type="CHANX" side="left" index="6"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="2" mux_size="4">
|
||||
<driver_node type="OPIN" side="top" index="1"/>
|
||||
<driver_node type="CHANX" side="right" index="3"/>
|
||||
<driver_node type="CHANX" side="right" index="19"/>
|
||||
<driver_node type="CHANX" side="left" index="2"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="4" mux_size="3">
|
||||
<driver_node type="OPIN" side="top" index="2"/>
|
||||
<driver_node type="CHANX" side="right" index="5"/>
|
||||
<driver_node type="CHANX" side="left" index="4"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="6" mux_size="3">
|
||||
<driver_node type="OPIN" side="top" index="3"/>
|
||||
<driver_node type="CHANX" side="right" index="9"/>
|
||||
<driver_node type="CHANX" side="left" index="8"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="8" mux_size="2">
|
||||
<driver_node type="CHANX" side="right" index="11"/>
|
||||
<driver_node type="CHANX" side="left" index="10"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="10" mux_size="2">
|
||||
<driver_node type="CHANX" side="right" index="13"/>
|
||||
<driver_node type="CHANX" side="left" index="12"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="12" mux_size="2">
|
||||
<driver_node type="CHANX" side="right" index="17"/>
|
||||
<driver_node type="CHANX" side="left" index="16"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="14" mux_size="0">
|
||||
<driver_node type="CHANY" side="bottom" index="-1"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="16" mux_size="1">
|
||||
<driver_node type="CHANX" side="left" index="18"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="18" mux_size="2">
|
||||
<driver_node type="CHANX" side="right" index="7"/>
|
||||
<driver_node type="CHANX" side="left" index="14"/>
|
||||
</CHANY>
|
||||
<CHANX side="right" index="0" mux_size="10">
|
||||
<driver_node type="CHANY" side="top" index="5"/>
|
||||
<driver_node type="CHANY" side="top" index="11"/>
|
||||
<driver_node type="CHANY" side="top" index="17"/>
|
||||
<driver_node type="OPIN" side="right" index="0"/>
|
||||
<driver_node type="OPIN" side="right" index="3"/>
|
||||
<driver_node type="OPIN" side="right" index="6"/>
|
||||
<driver_node type="OPIN" side="right" index="9"/>
|
||||
<driver_node type="CHANX" side="left" index="0"/>
|
||||
<driver_node type="CHANX" side="left" index="8"/>
|
||||
<driver_node type="CHANX" side="left" index="16"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="2" mux_size="0">
|
||||
<driver_node type="CHANX" side="left" index="0"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="4" mux_size="0">
|
||||
<driver_node type="CHANX" side="left" index="2"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="6" mux_size="0">
|
||||
<driver_node type="CHANX" side="left" index="4"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="8" mux_size="10">
|
||||
<driver_node type="CHANY" side="top" index="1"/>
|
||||
<driver_node type="CHANY" side="top" index="7"/>
|
||||
<driver_node type="CHANY" side="top" index="13"/>
|
||||
<driver_node type="CHANY" side="top" index="19"/>
|
||||
<driver_node type="OPIN" side="right" index="1"/>
|
||||
<driver_node type="OPIN" side="right" index="4"/>
|
||||
<driver_node type="OPIN" side="right" index="7"/>
|
||||
<driver_node type="OPIN" side="right" index="10"/>
|
||||
<driver_node type="CHANX" side="left" index="2"/>
|
||||
<driver_node type="CHANX" side="left" index="10"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="10" mux_size="0">
|
||||
<driver_node type="CHANX" side="left" index="8"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="12" mux_size="0">
|
||||
<driver_node type="CHANX" side="left" index="10"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="14" mux_size="0">
|
||||
<driver_node type="CHANX" side="left" index="12"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="16" mux_size="9">
|
||||
<driver_node type="CHANY" side="top" index="3"/>
|
||||
<driver_node type="CHANY" side="top" index="9"/>
|
||||
<driver_node type="CHANY" side="top" index="15"/>
|
||||
<driver_node type="OPIN" side="right" index="2"/>
|
||||
<driver_node type="OPIN" side="right" index="5"/>
|
||||
<driver_node type="OPIN" side="right" index="8"/>
|
||||
<driver_node type="OPIN" side="right" index="11"/>
|
||||
<driver_node type="CHANX" side="left" index="4"/>
|
||||
<driver_node type="CHANX" side="left" index="12"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="18" mux_size="0">
|
||||
<driver_node type="CHANX" side="left" index="16"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="1" mux_size="11">
|
||||
<driver_node type="CHANY" side="top" index="1"/>
|
||||
<driver_node type="CHANY" side="top" index="7"/>
|
||||
<driver_node type="CHANY" side="top" index="13"/>
|
||||
<driver_node type="CHANY" side="top" index="19"/>
|
||||
<driver_node type="CHANX" side="right" index="1"/>
|
||||
<driver_node type="CHANX" side="right" index="9"/>
|
||||
<driver_node type="CHANX" side="right" index="17"/>
|
||||
<driver_node type="OPIN" side="left" index="0"/>
|
||||
<driver_node type="OPIN" side="left" index="3"/>
|
||||
<driver_node type="OPIN" side="left" index="6"/>
|
||||
<driver_node type="OPIN" side="left" index="9"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="3" mux_size="0">
|
||||
<driver_node type="CHANX" side="right" index="1"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="5" mux_size="0">
|
||||
<driver_node type="CHANX" side="right" index="3"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="7" mux_size="0">
|
||||
<driver_node type="CHANX" side="right" index="5"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="9" mux_size="9">
|
||||
<driver_node type="CHANY" side="top" index="5"/>
|
||||
<driver_node type="CHANY" side="top" index="11"/>
|
||||
<driver_node type="CHANY" side="top" index="17"/>
|
||||
<driver_node type="CHANX" side="right" index="3"/>
|
||||
<driver_node type="CHANX" side="right" index="11"/>
|
||||
<driver_node type="OPIN" side="left" index="1"/>
|
||||
<driver_node type="OPIN" side="left" index="4"/>
|
||||
<driver_node type="OPIN" side="left" index="7"/>
|
||||
<driver_node type="OPIN" side="left" index="10"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="11" mux_size="0">
|
||||
<driver_node type="CHANX" side="right" index="9"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="13" mux_size="0">
|
||||
<driver_node type="CHANX" side="right" index="11"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="15" mux_size="0">
|
||||
<driver_node type="CHANX" side="right" index="13"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="17" mux_size="9">
|
||||
<driver_node type="CHANY" side="top" index="3"/>
|
||||
<driver_node type="CHANY" side="top" index="9"/>
|
||||
<driver_node type="CHANY" side="top" index="15"/>
|
||||
<driver_node type="CHANX" side="right" index="5"/>
|
||||
<driver_node type="CHANX" side="right" index="13"/>
|
||||
<driver_node type="OPIN" side="left" index="2"/>
|
||||
<driver_node type="OPIN" side="left" index="5"/>
|
||||
<driver_node type="OPIN" side="left" index="8"/>
|
||||
<driver_node type="OPIN" side="left" index="11"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="19" mux_size="0">
|
||||
<driver_node type="CHANX" side="right" index="17"/>
|
||||
</CHANX>
|
||||
</rr_sb>
|
||||
|
|
@ -0,0 +1,234 @@
|
|||
<rr_sb x="1" y="1" num_sides="4">
|
||||
<CHANY side="top" index="0" mux_size="13">
|
||||
<driver_node type="OPIN" side="top" index="0"/>
|
||||
<driver_node type="OPIN" side="top" index="3"/>
|
||||
<driver_node type="CHANX" side="right" index="1"/>
|
||||
<driver_node type="CHANX" side="right" index="9"/>
|
||||
<driver_node type="CHANX" side="right" index="15"/>
|
||||
<driver_node type="CHANX" side="right" index="17"/>
|
||||
<driver_node type="CHANY" side="bottom" index="0"/>
|
||||
<driver_node type="CHANY" side="bottom" index="8"/>
|
||||
<driver_node type="CHANY" side="bottom" index="16"/>
|
||||
<driver_node type="CHANX" side="left" index="0"/>
|
||||
<driver_node type="CHANX" side="left" index="6"/>
|
||||
<driver_node type="CHANX" side="left" index="8"/>
|
||||
<driver_node type="CHANX" side="left" index="16"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="2" mux_size="0">
|
||||
<driver_node type="CHANY" side="bottom" index="0"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="4" mux_size="0">
|
||||
<driver_node type="CHANY" side="bottom" index="2"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="6" mux_size="0">
|
||||
<driver_node type="CHANY" side="bottom" index="4"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="8" mux_size="9">
|
||||
<driver_node type="OPIN" side="top" index="1"/>
|
||||
<driver_node type="CHANX" side="right" index="3"/>
|
||||
<driver_node type="CHANX" side="right" index="11"/>
|
||||
<driver_node type="CHANX" side="right" index="19"/>
|
||||
<driver_node type="CHANY" side="bottom" index="2"/>
|
||||
<driver_node type="CHANY" side="bottom" index="10"/>
|
||||
<driver_node type="CHANX" side="left" index="2"/>
|
||||
<driver_node type="CHANX" side="left" index="10"/>
|
||||
<driver_node type="CHANX" side="left" index="18"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="10" mux_size="0">
|
||||
<driver_node type="CHANY" side="bottom" index="8"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="12" mux_size="0">
|
||||
<driver_node type="CHANY" side="bottom" index="10"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="14" mux_size="0">
|
||||
<driver_node type="CHANY" side="bottom" index="12"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="16" mux_size="9">
|
||||
<driver_node type="OPIN" side="top" index="2"/>
|
||||
<driver_node type="CHANX" side="right" index="5"/>
|
||||
<driver_node type="CHANX" side="right" index="7"/>
|
||||
<driver_node type="CHANX" side="right" index="13"/>
|
||||
<driver_node type="CHANY" side="bottom" index="4"/>
|
||||
<driver_node type="CHANY" side="bottom" index="12"/>
|
||||
<driver_node type="CHANX" side="left" index="4"/>
|
||||
<driver_node type="CHANX" side="left" index="12"/>
|
||||
<driver_node type="CHANX" side="left" index="14"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="18" mux_size="0">
|
||||
<driver_node type="CHANY" side="bottom" index="16"/>
|
||||
</CHANY>
|
||||
<CHANX side="right" index="0" mux_size="13">
|
||||
<driver_node type="CHANY" side="top" index="1"/>
|
||||
<driver_node type="CHANY" side="top" index="9"/>
|
||||
<driver_node type="CHANY" side="top" index="17"/>
|
||||
<driver_node type="CHANY" side="top" index="19"/>
|
||||
<driver_node type="OPIN" side="right" index="0"/>
|
||||
<driver_node type="OPIN" side="right" index="3"/>
|
||||
<driver_node type="CHANY" side="bottom" index="0"/>
|
||||
<driver_node type="CHANY" side="bottom" index="8"/>
|
||||
<driver_node type="CHANY" side="bottom" index="14"/>
|
||||
<driver_node type="CHANY" side="bottom" index="16"/>
|
||||
<driver_node type="CHANX" side="left" index="0"/>
|
||||
<driver_node type="CHANX" side="left" index="8"/>
|
||||
<driver_node type="CHANX" side="left" index="16"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="2" mux_size="0">
|
||||
<driver_node type="CHANX" side="left" index="0"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="4" mux_size="0">
|
||||
<driver_node type="CHANX" side="left" index="2"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="6" mux_size="0">
|
||||
<driver_node type="CHANX" side="left" index="4"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="8" mux_size="9">
|
||||
<driver_node type="CHANY" side="top" index="3"/>
|
||||
<driver_node type="CHANY" side="top" index="7"/>
|
||||
<driver_node type="CHANY" side="top" index="11"/>
|
||||
<driver_node type="OPIN" side="right" index="1"/>
|
||||
<driver_node type="CHANY" side="bottom" index="2"/>
|
||||
<driver_node type="CHANY" side="bottom" index="6"/>
|
||||
<driver_node type="CHANY" side="bottom" index="10"/>
|
||||
<driver_node type="CHANX" side="left" index="2"/>
|
||||
<driver_node type="CHANX" side="left" index="10"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="10" mux_size="0">
|
||||
<driver_node type="CHANX" side="left" index="8"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="12" mux_size="0">
|
||||
<driver_node type="CHANX" side="left" index="10"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="14" mux_size="0">
|
||||
<driver_node type="CHANX" side="left" index="12"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="16" mux_size="9">
|
||||
<driver_node type="CHANY" side="top" index="5"/>
|
||||
<driver_node type="CHANY" side="top" index="13"/>
|
||||
<driver_node type="CHANY" side="top" index="15"/>
|
||||
<driver_node type="OPIN" side="right" index="2"/>
|
||||
<driver_node type="CHANY" side="bottom" index="4"/>
|
||||
<driver_node type="CHANY" side="bottom" index="12"/>
|
||||
<driver_node type="CHANY" side="bottom" index="18"/>
|
||||
<driver_node type="CHANX" side="left" index="4"/>
|
||||
<driver_node type="CHANX" side="left" index="12"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="18" mux_size="0">
|
||||
<driver_node type="CHANX" side="left" index="16"/>
|
||||
</CHANX>
|
||||
<CHANY side="bottom" index="1" mux_size="13">
|
||||
<driver_node type="CHANY" side="top" index="1"/>
|
||||
<driver_node type="CHANY" side="top" index="9"/>
|
||||
<driver_node type="CHANY" side="top" index="17"/>
|
||||
<driver_node type="CHANX" side="right" index="1"/>
|
||||
<driver_node type="CHANX" side="right" index="9"/>
|
||||
<driver_node type="CHANX" side="right" index="15"/>
|
||||
<driver_node type="CHANX" side="right" index="17"/>
|
||||
<driver_node type="OPIN" side="bottom" index="0"/>
|
||||
<driver_node type="OPIN" side="bottom" index="3"/>
|
||||
<driver_node type="CHANX" side="left" index="0"/>
|
||||
<driver_node type="CHANX" side="left" index="8"/>
|
||||
<driver_node type="CHANX" side="left" index="14"/>
|
||||
<driver_node type="CHANX" side="left" index="16"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="3" mux_size="0">
|
||||
<driver_node type="CHANY" side="top" index="1"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="5" mux_size="0">
|
||||
<driver_node type="CHANY" side="top" index="3"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="7" mux_size="0">
|
||||
<driver_node type="CHANY" side="top" index="5"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="9" mux_size="9">
|
||||
<driver_node type="CHANY" side="top" index="3"/>
|
||||
<driver_node type="CHANY" side="top" index="11"/>
|
||||
<driver_node type="CHANX" side="right" index="3"/>
|
||||
<driver_node type="CHANX" side="right" index="7"/>
|
||||
<driver_node type="CHANX" side="right" index="11"/>
|
||||
<driver_node type="OPIN" side="bottom" index="1"/>
|
||||
<driver_node type="CHANX" side="left" index="2"/>
|
||||
<driver_node type="CHANX" side="left" index="10"/>
|
||||
<driver_node type="CHANX" side="left" index="18"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="11" mux_size="0">
|
||||
<driver_node type="CHANY" side="top" index="9"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="13" mux_size="0">
|
||||
<driver_node type="CHANY" side="top" index="11"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="15" mux_size="0">
|
||||
<driver_node type="CHANY" side="top" index="13"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="17" mux_size="9">
|
||||
<driver_node type="CHANY" side="top" index="5"/>
|
||||
<driver_node type="CHANY" side="top" index="13"/>
|
||||
<driver_node type="CHANX" side="right" index="5"/>
|
||||
<driver_node type="CHANX" side="right" index="13"/>
|
||||
<driver_node type="CHANX" side="right" index="19"/>
|
||||
<driver_node type="OPIN" side="bottom" index="2"/>
|
||||
<driver_node type="CHANX" side="left" index="4"/>
|
||||
<driver_node type="CHANX" side="left" index="6"/>
|
||||
<driver_node type="CHANX" side="left" index="12"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="19" mux_size="0">
|
||||
<driver_node type="CHANY" side="top" index="17"/>
|
||||
</CHANY>
|
||||
<CHANX side="left" index="1" mux_size="13">
|
||||
<driver_node type="CHANY" side="top" index="1"/>
|
||||
<driver_node type="CHANY" side="top" index="7"/>
|
||||
<driver_node type="CHANY" side="top" index="9"/>
|
||||
<driver_node type="CHANY" side="top" index="17"/>
|
||||
<driver_node type="CHANX" side="right" index="1"/>
|
||||
<driver_node type="CHANX" side="right" index="9"/>
|
||||
<driver_node type="CHANX" side="right" index="17"/>
|
||||
<driver_node type="CHANY" side="bottom" index="0"/>
|
||||
<driver_node type="CHANY" side="bottom" index="8"/>
|
||||
<driver_node type="CHANY" side="bottom" index="16"/>
|
||||
<driver_node type="CHANY" side="bottom" index="18"/>
|
||||
<driver_node type="OPIN" side="left" index="0"/>
|
||||
<driver_node type="OPIN" side="left" index="3"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="3" mux_size="0">
|
||||
<driver_node type="CHANX" side="right" index="1"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="5" mux_size="0">
|
||||
<driver_node type="CHANX" side="right" index="3"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="7" mux_size="0">
|
||||
<driver_node type="CHANX" side="right" index="5"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="9" mux_size="9">
|
||||
<driver_node type="CHANY" side="top" index="3"/>
|
||||
<driver_node type="CHANY" side="top" index="11"/>
|
||||
<driver_node type="CHANY" side="top" index="19"/>
|
||||
<driver_node type="CHANX" side="right" index="3"/>
|
||||
<driver_node type="CHANX" side="right" index="11"/>
|
||||
<driver_node type="CHANY" side="bottom" index="2"/>
|
||||
<driver_node type="CHANY" side="bottom" index="6"/>
|
||||
<driver_node type="CHANY" side="bottom" index="10"/>
|
||||
<driver_node type="OPIN" side="left" index="1"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="11" mux_size="0">
|
||||
<driver_node type="CHANX" side="right" index="9"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="13" mux_size="0">
|
||||
<driver_node type="CHANX" side="right" index="11"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="15" mux_size="0">
|
||||
<driver_node type="CHANX" side="right" index="13"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="17" mux_size="9">
|
||||
<driver_node type="CHANY" side="top" index="5"/>
|
||||
<driver_node type="CHANY" side="top" index="13"/>
|
||||
<driver_node type="CHANY" side="top" index="15"/>
|
||||
<driver_node type="CHANX" side="right" index="5"/>
|
||||
<driver_node type="CHANX" side="right" index="13"/>
|
||||
<driver_node type="CHANY" side="bottom" index="4"/>
|
||||
<driver_node type="CHANY" side="bottom" index="12"/>
|
||||
<driver_node type="CHANY" side="bottom" index="14"/>
|
||||
<driver_node type="OPIN" side="left" index="2"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="19" mux_size="0">
|
||||
<driver_node type="CHANX" side="right" index="17"/>
|
||||
</CHANX>
|
||||
</rr_sb>
|
||||
|
|
@ -0,0 +1,150 @@
|
|||
<rr_sb x="1" y="2" num_sides="4">
|
||||
<CHANX side="right" index="0" mux_size="9">
|
||||
<driver_node type="OPIN" side="right" index="0"/>
|
||||
<driver_node type="OPIN" side="right" index="3"/>
|
||||
<driver_node type="OPIN" side="right" index="6"/>
|
||||
<driver_node type="CHANY" side="bottom" index="2"/>
|
||||
<driver_node type="CHANY" side="bottom" index="8"/>
|
||||
<driver_node type="CHANY" side="bottom" index="14"/>
|
||||
<driver_node type="CHANX" side="left" index="0"/>
|
||||
<driver_node type="CHANX" side="left" index="8"/>
|
||||
<driver_node type="CHANX" side="left" index="16"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="2" mux_size="0">
|
||||
<driver_node type="CHANX" side="left" index="0"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="4" mux_size="0">
|
||||
<driver_node type="CHANX" side="left" index="2"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="6" mux_size="0">
|
||||
<driver_node type="CHANX" side="left" index="4"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="8" mux_size="9">
|
||||
<driver_node type="OPIN" side="right" index="1"/>
|
||||
<driver_node type="OPIN" side="right" index="4"/>
|
||||
<driver_node type="OPIN" side="right" index="7"/>
|
||||
<driver_node type="CHANY" side="bottom" index="0"/>
|
||||
<driver_node type="CHANY" side="bottom" index="6"/>
|
||||
<driver_node type="CHANY" side="bottom" index="12"/>
|
||||
<driver_node type="CHANY" side="bottom" index="18"/>
|
||||
<driver_node type="CHANX" side="left" index="2"/>
|
||||
<driver_node type="CHANX" side="left" index="10"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="10" mux_size="0">
|
||||
<driver_node type="CHANX" side="left" index="8"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="12" mux_size="0">
|
||||
<driver_node type="CHANX" side="left" index="10"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="14" mux_size="0">
|
||||
<driver_node type="CHANX" side="left" index="12"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="16" mux_size="7">
|
||||
<driver_node type="OPIN" side="right" index="2"/>
|
||||
<driver_node type="OPIN" side="right" index="5"/>
|
||||
<driver_node type="CHANY" side="bottom" index="4"/>
|
||||
<driver_node type="CHANY" side="bottom" index="10"/>
|
||||
<driver_node type="CHANY" side="bottom" index="16"/>
|
||||
<driver_node type="CHANX" side="left" index="4"/>
|
||||
<driver_node type="CHANX" side="left" index="12"/>
|
||||
</CHANX>
|
||||
<CHANX side="right" index="18" mux_size="0">
|
||||
<driver_node type="CHANX" side="left" index="16"/>
|
||||
</CHANX>
|
||||
<CHANY side="bottom" index="1" mux_size="4">
|
||||
<driver_node type="CHANX" side="right" index="1"/>
|
||||
<driver_node type="OPIN" side="bottom" index="0"/>
|
||||
<driver_node type="CHANX" side="left" index="0"/>
|
||||
<driver_node type="CHANX" side="left" index="14"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="3" mux_size="4">
|
||||
<driver_node type="CHANX" side="right" index="3"/>
|
||||
<driver_node type="OPIN" side="bottom" index="1"/>
|
||||
<driver_node type="CHANX" side="left" index="2"/>
|
||||
<driver_node type="CHANX" side="left" index="18"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="5" mux_size="3">
|
||||
<driver_node type="CHANX" side="right" index="5"/>
|
||||
<driver_node type="OPIN" side="bottom" index="2"/>
|
||||
<driver_node type="CHANX" side="left" index="4"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="7" mux_size="3">
|
||||
<driver_node type="CHANX" side="right" index="9"/>
|
||||
<driver_node type="OPIN" side="bottom" index="3"/>
|
||||
<driver_node type="CHANX" side="left" index="8"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="9" mux_size="2">
|
||||
<driver_node type="CHANX" side="right" index="11"/>
|
||||
<driver_node type="CHANX" side="left" index="10"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="11" mux_size="2">
|
||||
<driver_node type="CHANX" side="right" index="13"/>
|
||||
<driver_node type="CHANX" side="left" index="12"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="13" mux_size="3">
|
||||
<driver_node type="CHANX" side="right" index="17"/>
|
||||
<driver_node type="CHANX" side="right" index="19"/>
|
||||
<driver_node type="CHANX" side="left" index="16"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="15" mux_size="1">
|
||||
<driver_node type="CHANX" side="right" index="15"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="17" mux_size="1">
|
||||
<driver_node type="CHANX" side="right" index="7"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="19" mux_size="1">
|
||||
<driver_node type="CHANX" side="left" index="6"/>
|
||||
</CHANY>
|
||||
<CHANX side="left" index="1" mux_size="9">
|
||||
<driver_node type="CHANX" side="right" index="1"/>
|
||||
<driver_node type="CHANX" side="right" index="9"/>
|
||||
<driver_node type="CHANX" side="right" index="17"/>
|
||||
<driver_node type="CHANY" side="bottom" index="4"/>
|
||||
<driver_node type="CHANY" side="bottom" index="10"/>
|
||||
<driver_node type="CHANY" side="bottom" index="16"/>
|
||||
<driver_node type="OPIN" side="left" index="0"/>
|
||||
<driver_node type="OPIN" side="left" index="3"/>
|
||||
<driver_node type="OPIN" side="left" index="6"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="3" mux_size="0">
|
||||
<driver_node type="CHANX" side="right" index="1"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="5" mux_size="0">
|
||||
<driver_node type="CHANX" side="right" index="3"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="7" mux_size="0">
|
||||
<driver_node type="CHANX" side="right" index="5"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="9" mux_size="9">
|
||||
<driver_node type="CHANX" side="right" index="3"/>
|
||||
<driver_node type="CHANX" side="right" index="11"/>
|
||||
<driver_node type="CHANY" side="bottom" index="0"/>
|
||||
<driver_node type="CHANY" side="bottom" index="6"/>
|
||||
<driver_node type="CHANY" side="bottom" index="12"/>
|
||||
<driver_node type="CHANY" side="bottom" index="18"/>
|
||||
<driver_node type="OPIN" side="left" index="1"/>
|
||||
<driver_node type="OPIN" side="left" index="4"/>
|
||||
<driver_node type="OPIN" side="left" index="7"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="11" mux_size="0">
|
||||
<driver_node type="CHANX" side="right" index="9"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="13" mux_size="0">
|
||||
<driver_node type="CHANX" side="right" index="11"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="15" mux_size="0">
|
||||
<driver_node type="CHANX" side="right" index="13"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="17" mux_size="7">
|
||||
<driver_node type="CHANX" side="right" index="5"/>
|
||||
<driver_node type="CHANX" side="right" index="13"/>
|
||||
<driver_node type="CHANY" side="bottom" index="2"/>
|
||||
<driver_node type="CHANY" side="bottom" index="8"/>
|
||||
<driver_node type="CHANY" side="bottom" index="14"/>
|
||||
<driver_node type="OPIN" side="left" index="2"/>
|
||||
<driver_node type="OPIN" side="left" index="5"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="19" mux_size="0">
|
||||
<driver_node type="CHANX" side="right" index="17"/>
|
||||
</CHANX>
|
||||
</rr_sb>
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
<rr_sb x="2" y="0" num_sides="4">
|
||||
<CHANY side="top" index="0" mux_size="3">
|
||||
<driver_node type="OPIN" side="top" index="0"/>
|
||||
<driver_node type="OPIN" side="top" index="10"/>
|
||||
<driver_node type="CHANX" side="left" index="0"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="2" mux_size="3">
|
||||
<driver_node type="OPIN" side="top" index="1"/>
|
||||
<driver_node type="OPIN" side="top" index="11"/>
|
||||
<driver_node type="CHANX" side="left" index="18"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="4" mux_size="2">
|
||||
<driver_node type="OPIN" side="top" index="2"/>
|
||||
<driver_node type="CHANX" side="left" index="16"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="6" mux_size="2">
|
||||
<driver_node type="OPIN" side="top" index="3"/>
|
||||
<driver_node type="CHANX" side="left" index="14"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="8" mux_size="2">
|
||||
<driver_node type="OPIN" side="top" index="4"/>
|
||||
<driver_node type="CHANX" side="left" index="12"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="10" mux_size="2">
|
||||
<driver_node type="OPIN" side="top" index="5"/>
|
||||
<driver_node type="CHANX" side="left" index="10"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="12" mux_size="2">
|
||||
<driver_node type="OPIN" side="top" index="6"/>
|
||||
<driver_node type="CHANX" side="left" index="8"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="14" mux_size="2">
|
||||
<driver_node type="OPIN" side="top" index="7"/>
|
||||
<driver_node type="CHANX" side="left" index="6"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="16" mux_size="2">
|
||||
<driver_node type="OPIN" side="top" index="8"/>
|
||||
<driver_node type="CHANX" side="left" index="4"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="18" mux_size="2">
|
||||
<driver_node type="OPIN" side="top" index="9"/>
|
||||
<driver_node type="CHANX" side="left" index="2"/>
|
||||
</CHANY>
|
||||
<CHANX side="left" index="1" mux_size="3">
|
||||
<driver_node type="CHANY" side="top" index="1"/>
|
||||
<driver_node type="OPIN" side="left" index="0"/>
|
||||
<driver_node type="OPIN" side="left" index="10"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="3" mux_size="3">
|
||||
<driver_node type="CHANY" side="top" index="19"/>
|
||||
<driver_node type="OPIN" side="left" index="1"/>
|
||||
<driver_node type="OPIN" side="left" index="11"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="5" mux_size="2">
|
||||
<driver_node type="CHANY" side="top" index="17"/>
|
||||
<driver_node type="OPIN" side="left" index="2"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="7" mux_size="2">
|
||||
<driver_node type="CHANY" side="top" index="15"/>
|
||||
<driver_node type="OPIN" side="left" index="3"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="9" mux_size="2">
|
||||
<driver_node type="CHANY" side="top" index="13"/>
|
||||
<driver_node type="OPIN" side="left" index="4"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="11" mux_size="2">
|
||||
<driver_node type="CHANY" side="top" index="11"/>
|
||||
<driver_node type="OPIN" side="left" index="5"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="13" mux_size="2">
|
||||
<driver_node type="CHANY" side="top" index="9"/>
|
||||
<driver_node type="OPIN" side="left" index="6"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="15" mux_size="2">
|
||||
<driver_node type="CHANY" side="top" index="7"/>
|
||||
<driver_node type="OPIN" side="left" index="7"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="17" mux_size="2">
|
||||
<driver_node type="CHANY" side="top" index="5"/>
|
||||
<driver_node type="OPIN" side="left" index="8"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="19" mux_size="2">
|
||||
<driver_node type="CHANY" side="top" index="3"/>
|
||||
<driver_node type="OPIN" side="left" index="9"/>
|
||||
</CHANX>
|
||||
</rr_sb>
|
||||
|
|
@ -0,0 +1,159 @@
|
|||
<rr_sb x="2" y="1" num_sides="4">
|
||||
<CHANY side="top" index="0" mux_size="11">
|
||||
<driver_node type="OPIN" side="top" index="0"/>
|
||||
<driver_node type="OPIN" side="top" index="3"/>
|
||||
<driver_node type="OPIN" side="top" index="6"/>
|
||||
<driver_node type="OPIN" side="top" index="9"/>
|
||||
<driver_node type="CHANY" side="bottom" index="0"/>
|
||||
<driver_node type="CHANY" side="bottom" index="8"/>
|
||||
<driver_node type="CHANY" side="bottom" index="16"/>
|
||||
<driver_node type="CHANX" side="left" index="0"/>
|
||||
<driver_node type="CHANX" side="left" index="6"/>
|
||||
<driver_node type="CHANX" side="left" index="12"/>
|
||||
<driver_node type="CHANX" side="left" index="18"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="2" mux_size="0">
|
||||
<driver_node type="CHANY" side="bottom" index="0"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="4" mux_size="0">
|
||||
<driver_node type="CHANY" side="bottom" index="2"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="6" mux_size="0">
|
||||
<driver_node type="CHANY" side="bottom" index="4"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="8" mux_size="9">
|
||||
<driver_node type="OPIN" side="top" index="1"/>
|
||||
<driver_node type="OPIN" side="top" index="4"/>
|
||||
<driver_node type="OPIN" side="top" index="7"/>
|
||||
<driver_node type="OPIN" side="top" index="10"/>
|
||||
<driver_node type="CHANY" side="bottom" index="2"/>
|
||||
<driver_node type="CHANY" side="bottom" index="10"/>
|
||||
<driver_node type="CHANX" side="left" index="4"/>
|
||||
<driver_node type="CHANX" side="left" index="10"/>
|
||||
<driver_node type="CHANX" side="left" index="16"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="10" mux_size="0">
|
||||
<driver_node type="CHANY" side="bottom" index="8"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="12" mux_size="0">
|
||||
<driver_node type="CHANY" side="bottom" index="10"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="14" mux_size="0">
|
||||
<driver_node type="CHANY" side="bottom" index="12"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="16" mux_size="9">
|
||||
<driver_node type="OPIN" side="top" index="2"/>
|
||||
<driver_node type="OPIN" side="top" index="5"/>
|
||||
<driver_node type="OPIN" side="top" index="8"/>
|
||||
<driver_node type="OPIN" side="top" index="11"/>
|
||||
<driver_node type="CHANY" side="bottom" index="4"/>
|
||||
<driver_node type="CHANY" side="bottom" index="12"/>
|
||||
<driver_node type="CHANX" side="left" index="2"/>
|
||||
<driver_node type="CHANX" side="left" index="8"/>
|
||||
<driver_node type="CHANX" side="left" index="14"/>
|
||||
</CHANY>
|
||||
<CHANY side="top" index="18" mux_size="0">
|
||||
<driver_node type="CHANY" side="bottom" index="16"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="1" mux_size="10">
|
||||
<driver_node type="CHANY" side="top" index="1"/>
|
||||
<driver_node type="CHANY" side="top" index="9"/>
|
||||
<driver_node type="CHANY" side="top" index="17"/>
|
||||
<driver_node type="OPIN" side="bottom" index="0"/>
|
||||
<driver_node type="OPIN" side="bottom" index="3"/>
|
||||
<driver_node type="OPIN" side="bottom" index="6"/>
|
||||
<driver_node type="OPIN" side="bottom" index="9"/>
|
||||
<driver_node type="CHANX" side="left" index="2"/>
|
||||
<driver_node type="CHANX" side="left" index="8"/>
|
||||
<driver_node type="CHANX" side="left" index="14"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="3" mux_size="0">
|
||||
<driver_node type="CHANY" side="top" index="1"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="5" mux_size="0">
|
||||
<driver_node type="CHANY" side="top" index="3"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="7" mux_size="0">
|
||||
<driver_node type="CHANY" side="top" index="5"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="9" mux_size="9">
|
||||
<driver_node type="CHANY" side="top" index="3"/>
|
||||
<driver_node type="CHANY" side="top" index="11"/>
|
||||
<driver_node type="OPIN" side="bottom" index="1"/>
|
||||
<driver_node type="OPIN" side="bottom" index="4"/>
|
||||
<driver_node type="OPIN" side="bottom" index="7"/>
|
||||
<driver_node type="OPIN" side="bottom" index="10"/>
|
||||
<driver_node type="CHANX" side="left" index="4"/>
|
||||
<driver_node type="CHANX" side="left" index="10"/>
|
||||
<driver_node type="CHANX" side="left" index="16"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="11" mux_size="0">
|
||||
<driver_node type="CHANY" side="top" index="9"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="13" mux_size="0">
|
||||
<driver_node type="CHANY" side="top" index="11"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="15" mux_size="0">
|
||||
<driver_node type="CHANY" side="top" index="13"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="17" mux_size="10">
|
||||
<driver_node type="CHANY" side="top" index="5"/>
|
||||
<driver_node type="CHANY" side="top" index="13"/>
|
||||
<driver_node type="OPIN" side="bottom" index="2"/>
|
||||
<driver_node type="OPIN" side="bottom" index="5"/>
|
||||
<driver_node type="OPIN" side="bottom" index="8"/>
|
||||
<driver_node type="OPIN" side="bottom" index="11"/>
|
||||
<driver_node type="CHANX" side="left" index="0"/>
|
||||
<driver_node type="CHANX" side="left" index="6"/>
|
||||
<driver_node type="CHANX" side="left" index="12"/>
|
||||
<driver_node type="CHANX" side="left" index="18"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="19" mux_size="0">
|
||||
<driver_node type="CHANY" side="top" index="17"/>
|
||||
</CHANY>
|
||||
<CHANX side="left" index="1" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="1"/>
|
||||
<driver_node type="CHANY" side="top" index="7"/>
|
||||
<driver_node type="CHANY" side="bottom" index="0"/>
|
||||
<driver_node type="OPIN" side="left" index="0"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="3" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="3"/>
|
||||
<driver_node type="CHANY" side="bottom" index="2"/>
|
||||
<driver_node type="CHANY" side="bottom" index="6"/>
|
||||
<driver_node type="OPIN" side="left" index="1"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="5" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="5"/>
|
||||
<driver_node type="CHANY" side="bottom" index="4"/>
|
||||
<driver_node type="CHANY" side="bottom" index="14"/>
|
||||
<driver_node type="OPIN" side="left" index="2"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="7" mux_size="4">
|
||||
<driver_node type="CHANY" side="top" index="9"/>
|
||||
<driver_node type="CHANY" side="bottom" index="8"/>
|
||||
<driver_node type="CHANY" side="bottom" index="18"/>
|
||||
<driver_node type="OPIN" side="left" index="3"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="9" mux_size="2">
|
||||
<driver_node type="CHANY" side="top" index="11"/>
|
||||
<driver_node type="CHANY" side="bottom" index="10"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="11" mux_size="2">
|
||||
<driver_node type="CHANY" side="top" index="13"/>
|
||||
<driver_node type="CHANY" side="bottom" index="12"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="13" mux_size="2">
|
||||
<driver_node type="CHANY" side="top" index="17"/>
|
||||
<driver_node type="CHANY" side="bottom" index="16"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="15" mux_size="0">
|
||||
<driver_node type="CHANX" side="right" index="-1"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="17" mux_size="1">
|
||||
<driver_node type="CHANY" side="top" index="19"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="19" mux_size="1">
|
||||
<driver_node type="CHANY" side="top" index="15"/>
|
||||
</CHANX>
|
||||
</rr_sb>
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
<rr_sb x="2" y="2" num_sides="4">
|
||||
<CHANY side="bottom" index="1" mux_size="3">
|
||||
<driver_node type="OPIN" side="bottom" index="0"/>
|
||||
<driver_node type="OPIN" side="bottom" index="10"/>
|
||||
<driver_node type="CHANX" side="left" index="2"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="3" mux_size="3">
|
||||
<driver_node type="OPIN" side="bottom" index="1"/>
|
||||
<driver_node type="OPIN" side="bottom" index="11"/>
|
||||
<driver_node type="CHANX" side="left" index="4"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="5" mux_size="2">
|
||||
<driver_node type="OPIN" side="bottom" index="2"/>
|
||||
<driver_node type="CHANX" side="left" index="6"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="7" mux_size="2">
|
||||
<driver_node type="OPIN" side="bottom" index="3"/>
|
||||
<driver_node type="CHANX" side="left" index="8"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="9" mux_size="2">
|
||||
<driver_node type="OPIN" side="bottom" index="4"/>
|
||||
<driver_node type="CHANX" side="left" index="10"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="11" mux_size="2">
|
||||
<driver_node type="OPIN" side="bottom" index="5"/>
|
||||
<driver_node type="CHANX" side="left" index="12"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="13" mux_size="2">
|
||||
<driver_node type="OPIN" side="bottom" index="6"/>
|
||||
<driver_node type="CHANX" side="left" index="14"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="15" mux_size="2">
|
||||
<driver_node type="OPIN" side="bottom" index="7"/>
|
||||
<driver_node type="CHANX" side="left" index="16"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="17" mux_size="2">
|
||||
<driver_node type="OPIN" side="bottom" index="8"/>
|
||||
<driver_node type="CHANX" side="left" index="18"/>
|
||||
</CHANY>
|
||||
<CHANY side="bottom" index="19" mux_size="2">
|
||||
<driver_node type="OPIN" side="bottom" index="9"/>
|
||||
<driver_node type="CHANX" side="left" index="0"/>
|
||||
</CHANY>
|
||||
<CHANX side="left" index="1" mux_size="2">
|
||||
<driver_node type="CHANY" side="bottom" index="18"/>
|
||||
<driver_node type="OPIN" side="left" index="0"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="3" mux_size="2">
|
||||
<driver_node type="CHANY" side="bottom" index="0"/>
|
||||
<driver_node type="OPIN" side="left" index="1"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="5" mux_size="2">
|
||||
<driver_node type="CHANY" side="bottom" index="2"/>
|
||||
<driver_node type="OPIN" side="left" index="2"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="7" mux_size="2">
|
||||
<driver_node type="CHANY" side="bottom" index="4"/>
|
||||
<driver_node type="OPIN" side="left" index="3"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="9" mux_size="2">
|
||||
<driver_node type="CHANY" side="bottom" index="6"/>
|
||||
<driver_node type="OPIN" side="left" index="4"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="11" mux_size="2">
|
||||
<driver_node type="CHANY" side="bottom" index="8"/>
|
||||
<driver_node type="OPIN" side="left" index="5"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="13" mux_size="2">
|
||||
<driver_node type="CHANY" side="bottom" index="10"/>
|
||||
<driver_node type="OPIN" side="left" index="6"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="15" mux_size="2">
|
||||
<driver_node type="CHANY" side="bottom" index="12"/>
|
||||
<driver_node type="OPIN" side="left" index="7"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="17" mux_size="1">
|
||||
<driver_node type="CHANY" side="bottom" index="14"/>
|
||||
</CHANX>
|
||||
<CHANX side="left" index="19" mux_size="1">
|
||||
<driver_node type="CHANY" side="bottom" index="16"/>
|
||||
</CHANX>
|
||||
</rr_sb>
|
||||
|
|
@ -0,0 +1,143 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for physical tile: clb]
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ----- BEGIN Grid Verilog module: grid_clb -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for grid_clb -----
|
||||
module grid_clb(pReset,
|
||||
prog_clk,
|
||||
set,
|
||||
reset,
|
||||
clk,
|
||||
top_width_0_height_0_subtile_0__pin_cin_0_,
|
||||
right_width_0_height_0_subtile_0__pin_I_0_,
|
||||
right_width_0_height_0_subtile_0__pin_I_1_,
|
||||
right_width_0_height_0_subtile_0__pin_I_2_,
|
||||
right_width_0_height_0_subtile_0__pin_I_3_,
|
||||
right_width_0_height_0_subtile_0__pin_I_4_,
|
||||
right_width_0_height_0_subtile_0__pin_I_5_,
|
||||
bottom_width_0_height_0_subtile_0__pin_I_6_,
|
||||
bottom_width_0_height_0_subtile_0__pin_I_7_,
|
||||
bottom_width_0_height_0_subtile_0__pin_I_8_,
|
||||
bottom_width_0_height_0_subtile_0__pin_I_9_,
|
||||
bottom_width_0_height_0_subtile_0__pin_I_10_,
|
||||
bottom_width_0_height_0_subtile_0__pin_I_11_,
|
||||
left_width_0_height_0_subtile_0__pin_clk_0_,
|
||||
ccff_head,
|
||||
right_width_0_height_0_subtile_0__pin_O_0_,
|
||||
right_width_0_height_0_subtile_0__pin_O_1_,
|
||||
right_width_0_height_0_subtile_0__pin_O_2_,
|
||||
right_width_0_height_0_subtile_0__pin_O_3_,
|
||||
bottom_width_0_height_0_subtile_0__pin_O_4_,
|
||||
bottom_width_0_height_0_subtile_0__pin_O_5_,
|
||||
bottom_width_0_height_0_subtile_0__pin_O_6_,
|
||||
bottom_width_0_height_0_subtile_0__pin_O_7_,
|
||||
bottom_width_0_height_0_subtile_0__pin_cout_0_,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] pReset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] set;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] reset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_width_0_height_0_subtile_0__pin_cin_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_0__pin_I_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_0__pin_I_1_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_0__pin_I_2_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_0__pin_I_3_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_0__pin_I_4_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_0__pin_I_5_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_0__pin_I_6_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_0__pin_I_7_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_0__pin_I_8_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_0__pin_I_9_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_0__pin_I_10_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_0__pin_I_11_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_width_0_height_0_subtile_0__pin_clk_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_width_0_height_0_subtile_0__pin_O_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_width_0_height_0_subtile_0__pin_O_1_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_width_0_height_0_subtile_0__pin_O_2_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_width_0_height_0_subtile_0__pin_O_3_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_width_0_height_0_subtile_0__pin_O_4_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_width_0_height_0_subtile_0__pin_O_5_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_width_0_height_0_subtile_0__pin_O_6_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_width_0_height_0_subtile_0__pin_O_7_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_width_0_height_0_subtile_0__pin_cout_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.set(set),
|
||||
.reset(reset),
|
||||
.clk(clk),
|
||||
.clb_I({right_width_0_height_0_subtile_0__pin_I_0_, right_width_0_height_0_subtile_0__pin_I_1_, right_width_0_height_0_subtile_0__pin_I_2_, right_width_0_height_0_subtile_0__pin_I_3_, right_width_0_height_0_subtile_0__pin_I_4_, right_width_0_height_0_subtile_0__pin_I_5_, bottom_width_0_height_0_subtile_0__pin_I_6_, bottom_width_0_height_0_subtile_0__pin_I_7_, bottom_width_0_height_0_subtile_0__pin_I_8_, bottom_width_0_height_0_subtile_0__pin_I_9_, bottom_width_0_height_0_subtile_0__pin_I_10_, bottom_width_0_height_0_subtile_0__pin_I_11_}),
|
||||
.clb_cin(top_width_0_height_0_subtile_0__pin_cin_0_),
|
||||
.clb_clk(left_width_0_height_0_subtile_0__pin_clk_0_),
|
||||
.ccff_head(ccff_head),
|
||||
.clb_O({right_width_0_height_0_subtile_0__pin_O_0_, right_width_0_height_0_subtile_0__pin_O_1_, right_width_0_height_0_subtile_0__pin_O_2_, right_width_0_height_0_subtile_0__pin_O_3_, bottom_width_0_height_0_subtile_0__pin_O_4_, bottom_width_0_height_0_subtile_0__pin_O_5_, bottom_width_0_height_0_subtile_0__pin_O_6_, bottom_width_0_height_0_subtile_0__pin_O_7_}),
|
||||
.clb_cout(bottom_width_0_height_0_subtile_0__pin_cout_0_),
|
||||
.ccff_tail(ccff_tail));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for grid_clb -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
// ----- END Grid Verilog module: grid_clb -----
|
||||
|
||||
|
|
@ -0,0 +1,181 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for physical tile: io]
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ----- BEGIN Grid Verilog module: grid_io_bottom -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for grid_io_bottom -----
|
||||
module grid_io_bottom(pReset,
|
||||
prog_clk,
|
||||
gfpga_pad_GPIO_PAD,
|
||||
top_width_0_height_0_subtile_0__pin_outpad_0_,
|
||||
top_width_0_height_0_subtile_1__pin_outpad_0_,
|
||||
top_width_0_height_0_subtile_2__pin_outpad_0_,
|
||||
top_width_0_height_0_subtile_3__pin_outpad_0_,
|
||||
top_width_0_height_0_subtile_4__pin_outpad_0_,
|
||||
top_width_0_height_0_subtile_5__pin_outpad_0_,
|
||||
top_width_0_height_0_subtile_6__pin_outpad_0_,
|
||||
top_width_0_height_0_subtile_7__pin_outpad_0_,
|
||||
ccff_head,
|
||||
top_width_0_height_0_subtile_0__pin_inpad_0_,
|
||||
top_width_0_height_0_subtile_1__pin_inpad_0_,
|
||||
top_width_0_height_0_subtile_2__pin_inpad_0_,
|
||||
top_width_0_height_0_subtile_3__pin_inpad_0_,
|
||||
top_width_0_height_0_subtile_4__pin_inpad_0_,
|
||||
top_width_0_height_0_subtile_5__pin_inpad_0_,
|
||||
top_width_0_height_0_subtile_6__pin_inpad_0_,
|
||||
top_width_0_height_0_subtile_7__pin_inpad_0_,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] pReset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- GPIO PORTS -----
|
||||
inout [0:7] gfpga_pad_GPIO_PAD;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_width_0_height_0_subtile_0__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_width_0_height_0_subtile_1__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_width_0_height_0_subtile_2__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_width_0_height_0_subtile_3__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_width_0_height_0_subtile_4__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_width_0_height_0_subtile_5__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_width_0_height_0_subtile_6__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] top_width_0_height_0_subtile_7__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_width_0_height_0_subtile_4__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_width_0_height_0_subtile_5__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_width_0_height_0_subtile_6__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] top_width_0_height_0_subtile_7__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]),
|
||||
.io_outpad(top_width_0_height_0_subtile_0__pin_outpad_0_),
|
||||
.ccff_head(ccff_head),
|
||||
.io_inpad(top_width_0_height_0_subtile_0__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]),
|
||||
.io_outpad(top_width_0_height_0_subtile_1__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
|
||||
.io_inpad(top_width_0_height_0_subtile_1__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]),
|
||||
.io_outpad(top_width_0_height_0_subtile_2__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
|
||||
.io_inpad(top_width_0_height_0_subtile_2__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]),
|
||||
.io_outpad(top_width_0_height_0_subtile_3__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
|
||||
.io_inpad(top_width_0_height_0_subtile_3__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]),
|
||||
.io_outpad(top_width_0_height_0_subtile_4__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__3_ccff_tail),
|
||||
.io_inpad(top_width_0_height_0_subtile_4__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]),
|
||||
.io_outpad(top_width_0_height_0_subtile_5__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__4_ccff_tail),
|
||||
.io_inpad(top_width_0_height_0_subtile_5__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__5_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]),
|
||||
.io_outpad(top_width_0_height_0_subtile_6__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__5_ccff_tail),
|
||||
.io_inpad(top_width_0_height_0_subtile_6__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__6_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]),
|
||||
.io_outpad(top_width_0_height_0_subtile_7__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__6_ccff_tail),
|
||||
.io_inpad(top_width_0_height_0_subtile_7__pin_inpad_0_),
|
||||
.ccff_tail(ccff_tail));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for grid_io_bottom -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
// ----- END Grid Verilog module: grid_io_bottom -----
|
||||
|
||||
|
|
@ -0,0 +1,181 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for physical tile: io]
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ----- BEGIN Grid Verilog module: grid_io_left -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for grid_io_left -----
|
||||
module grid_io_left(pReset,
|
||||
prog_clk,
|
||||
gfpga_pad_GPIO_PAD,
|
||||
right_width_0_height_0_subtile_0__pin_outpad_0_,
|
||||
right_width_0_height_0_subtile_1__pin_outpad_0_,
|
||||
right_width_0_height_0_subtile_2__pin_outpad_0_,
|
||||
right_width_0_height_0_subtile_3__pin_outpad_0_,
|
||||
right_width_0_height_0_subtile_4__pin_outpad_0_,
|
||||
right_width_0_height_0_subtile_5__pin_outpad_0_,
|
||||
right_width_0_height_0_subtile_6__pin_outpad_0_,
|
||||
right_width_0_height_0_subtile_7__pin_outpad_0_,
|
||||
ccff_head,
|
||||
right_width_0_height_0_subtile_0__pin_inpad_0_,
|
||||
right_width_0_height_0_subtile_1__pin_inpad_0_,
|
||||
right_width_0_height_0_subtile_2__pin_inpad_0_,
|
||||
right_width_0_height_0_subtile_3__pin_inpad_0_,
|
||||
right_width_0_height_0_subtile_4__pin_inpad_0_,
|
||||
right_width_0_height_0_subtile_5__pin_inpad_0_,
|
||||
right_width_0_height_0_subtile_6__pin_inpad_0_,
|
||||
right_width_0_height_0_subtile_7__pin_inpad_0_,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] pReset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- GPIO PORTS -----
|
||||
inout [0:7] gfpga_pad_GPIO_PAD;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_0__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_1__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_2__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_3__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_4__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_5__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_6__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] right_width_0_height_0_subtile_7__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_width_0_height_0_subtile_4__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_width_0_height_0_subtile_5__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_width_0_height_0_subtile_6__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] right_width_0_height_0_subtile_7__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]),
|
||||
.io_outpad(right_width_0_height_0_subtile_0__pin_outpad_0_),
|
||||
.ccff_head(ccff_head),
|
||||
.io_inpad(right_width_0_height_0_subtile_0__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]),
|
||||
.io_outpad(right_width_0_height_0_subtile_1__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
|
||||
.io_inpad(right_width_0_height_0_subtile_1__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]),
|
||||
.io_outpad(right_width_0_height_0_subtile_2__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
|
||||
.io_inpad(right_width_0_height_0_subtile_2__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]),
|
||||
.io_outpad(right_width_0_height_0_subtile_3__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
|
||||
.io_inpad(right_width_0_height_0_subtile_3__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]),
|
||||
.io_outpad(right_width_0_height_0_subtile_4__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__3_ccff_tail),
|
||||
.io_inpad(right_width_0_height_0_subtile_4__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]),
|
||||
.io_outpad(right_width_0_height_0_subtile_5__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__4_ccff_tail),
|
||||
.io_inpad(right_width_0_height_0_subtile_5__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__5_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]),
|
||||
.io_outpad(right_width_0_height_0_subtile_6__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__5_ccff_tail),
|
||||
.io_inpad(right_width_0_height_0_subtile_6__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__6_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]),
|
||||
.io_outpad(right_width_0_height_0_subtile_7__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__6_ccff_tail),
|
||||
.io_inpad(right_width_0_height_0_subtile_7__pin_inpad_0_),
|
||||
.ccff_tail(ccff_tail));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for grid_io_left -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
// ----- END Grid Verilog module: grid_io_left -----
|
||||
|
||||
|
|
@ -0,0 +1,181 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for physical tile: io]
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ----- BEGIN Grid Verilog module: grid_io_right -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for grid_io_right -----
|
||||
module grid_io_right(pReset,
|
||||
prog_clk,
|
||||
gfpga_pad_GPIO_PAD,
|
||||
left_width_0_height_0_subtile_0__pin_outpad_0_,
|
||||
left_width_0_height_0_subtile_1__pin_outpad_0_,
|
||||
left_width_0_height_0_subtile_2__pin_outpad_0_,
|
||||
left_width_0_height_0_subtile_3__pin_outpad_0_,
|
||||
left_width_0_height_0_subtile_4__pin_outpad_0_,
|
||||
left_width_0_height_0_subtile_5__pin_outpad_0_,
|
||||
left_width_0_height_0_subtile_6__pin_outpad_0_,
|
||||
left_width_0_height_0_subtile_7__pin_outpad_0_,
|
||||
ccff_head,
|
||||
left_width_0_height_0_subtile_0__pin_inpad_0_,
|
||||
left_width_0_height_0_subtile_1__pin_inpad_0_,
|
||||
left_width_0_height_0_subtile_2__pin_inpad_0_,
|
||||
left_width_0_height_0_subtile_3__pin_inpad_0_,
|
||||
left_width_0_height_0_subtile_4__pin_inpad_0_,
|
||||
left_width_0_height_0_subtile_5__pin_inpad_0_,
|
||||
left_width_0_height_0_subtile_6__pin_inpad_0_,
|
||||
left_width_0_height_0_subtile_7__pin_inpad_0_,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] pReset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- GPIO PORTS -----
|
||||
inout [0:7] gfpga_pad_GPIO_PAD;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_width_0_height_0_subtile_0__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_width_0_height_0_subtile_1__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_width_0_height_0_subtile_2__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_width_0_height_0_subtile_3__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_width_0_height_0_subtile_4__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_width_0_height_0_subtile_5__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_width_0_height_0_subtile_6__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] left_width_0_height_0_subtile_7__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_width_0_height_0_subtile_4__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_width_0_height_0_subtile_5__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_width_0_height_0_subtile_6__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] left_width_0_height_0_subtile_7__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]),
|
||||
.io_outpad(left_width_0_height_0_subtile_0__pin_outpad_0_),
|
||||
.ccff_head(ccff_head),
|
||||
.io_inpad(left_width_0_height_0_subtile_0__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]),
|
||||
.io_outpad(left_width_0_height_0_subtile_1__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
|
||||
.io_inpad(left_width_0_height_0_subtile_1__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]),
|
||||
.io_outpad(left_width_0_height_0_subtile_2__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
|
||||
.io_inpad(left_width_0_height_0_subtile_2__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]),
|
||||
.io_outpad(left_width_0_height_0_subtile_3__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
|
||||
.io_inpad(left_width_0_height_0_subtile_3__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]),
|
||||
.io_outpad(left_width_0_height_0_subtile_4__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__3_ccff_tail),
|
||||
.io_inpad(left_width_0_height_0_subtile_4__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]),
|
||||
.io_outpad(left_width_0_height_0_subtile_5__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__4_ccff_tail),
|
||||
.io_inpad(left_width_0_height_0_subtile_5__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__5_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]),
|
||||
.io_outpad(left_width_0_height_0_subtile_6__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__5_ccff_tail),
|
||||
.io_inpad(left_width_0_height_0_subtile_6__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__6_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]),
|
||||
.io_outpad(left_width_0_height_0_subtile_7__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__6_ccff_tail),
|
||||
.io_inpad(left_width_0_height_0_subtile_7__pin_inpad_0_),
|
||||
.ccff_tail(ccff_tail));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for grid_io_right -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
// ----- END Grid Verilog module: grid_io_right -----
|
||||
|
||||
|
|
@ -0,0 +1,181 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for physical tile: io]
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ----- BEGIN Grid Verilog module: grid_io_top -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for grid_io_top -----
|
||||
module grid_io_top(pReset,
|
||||
prog_clk,
|
||||
gfpga_pad_GPIO_PAD,
|
||||
bottom_width_0_height_0_subtile_0__pin_outpad_0_,
|
||||
bottom_width_0_height_0_subtile_1__pin_outpad_0_,
|
||||
bottom_width_0_height_0_subtile_2__pin_outpad_0_,
|
||||
bottom_width_0_height_0_subtile_3__pin_outpad_0_,
|
||||
bottom_width_0_height_0_subtile_4__pin_outpad_0_,
|
||||
bottom_width_0_height_0_subtile_5__pin_outpad_0_,
|
||||
bottom_width_0_height_0_subtile_6__pin_outpad_0_,
|
||||
bottom_width_0_height_0_subtile_7__pin_outpad_0_,
|
||||
ccff_head,
|
||||
bottom_width_0_height_0_subtile_0__pin_inpad_0_,
|
||||
bottom_width_0_height_0_subtile_1__pin_inpad_0_,
|
||||
bottom_width_0_height_0_subtile_2__pin_inpad_0_,
|
||||
bottom_width_0_height_0_subtile_3__pin_inpad_0_,
|
||||
bottom_width_0_height_0_subtile_4__pin_inpad_0_,
|
||||
bottom_width_0_height_0_subtile_5__pin_inpad_0_,
|
||||
bottom_width_0_height_0_subtile_6__pin_inpad_0_,
|
||||
bottom_width_0_height_0_subtile_7__pin_inpad_0_,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] pReset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- GPIO PORTS -----
|
||||
inout [0:7] gfpga_pad_GPIO_PAD;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_0__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_1__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_2__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_3__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_4__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_5__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_6__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] bottom_width_0_height_0_subtile_7__pin_outpad_0_;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_width_0_height_0_subtile_4__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_width_0_height_0_subtile_5__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_width_0_height_0_subtile_6__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] bottom_width_0_height_0_subtile_7__pin_inpad_0_;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]),
|
||||
.io_outpad(bottom_width_0_height_0_subtile_0__pin_outpad_0_),
|
||||
.ccff_head(ccff_head),
|
||||
.io_inpad(bottom_width_0_height_0_subtile_0__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]),
|
||||
.io_outpad(bottom_width_0_height_0_subtile_1__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
|
||||
.io_inpad(bottom_width_0_height_0_subtile_1__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]),
|
||||
.io_outpad(bottom_width_0_height_0_subtile_2__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
|
||||
.io_inpad(bottom_width_0_height_0_subtile_2__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]),
|
||||
.io_outpad(bottom_width_0_height_0_subtile_3__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
|
||||
.io_inpad(bottom_width_0_height_0_subtile_3__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]),
|
||||
.io_outpad(bottom_width_0_height_0_subtile_4__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__3_ccff_tail),
|
||||
.io_inpad(bottom_width_0_height_0_subtile_4__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]),
|
||||
.io_outpad(bottom_width_0_height_0_subtile_5__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__4_ccff_tail),
|
||||
.io_inpad(bottom_width_0_height_0_subtile_5__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__5_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]),
|
||||
.io_outpad(bottom_width_0_height_0_subtile_6__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__5_ccff_tail),
|
||||
.io_inpad(bottom_width_0_height_0_subtile_6__pin_inpad_0_),
|
||||
.ccff_tail(logical_tile_io_mode_io__6_ccff_tail));
|
||||
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]),
|
||||
.io_outpad(bottom_width_0_height_0_subtile_7__pin_outpad_0_),
|
||||
.ccff_head(logical_tile_io_mode_io__6_ccff_tail),
|
||||
.io_inpad(bottom_width_0_height_0_subtile_7__pin_inpad_0_),
|
||||
.ccff_tail(ccff_tail));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for grid_io_top -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
// ----- END Grid Verilog module: grid_io_top -----
|
||||
|
||||
|
|
@ -0,0 +1,510 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for pb_type: clb
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ----- BEGIN Physical programmable logic block Verilog module: clb -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for logical_tile_clb_mode_clb_ -----
|
||||
module logical_tile_clb_mode_clb_(pReset,
|
||||
prog_clk,
|
||||
set,
|
||||
reset,
|
||||
clk,
|
||||
clb_I,
|
||||
clb_cin,
|
||||
clb_clk,
|
||||
ccff_head,
|
||||
clb_O,
|
||||
clb_cout,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] pReset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] set;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] reset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:11] clb_I;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] clb_cin;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] clb_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:7] clb_O;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] clb_cout;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
wire [0:11] clb_I;
|
||||
wire [0:0] clb_cin;
|
||||
wire [0:0] clb_clk;
|
||||
wire [0:7] clb_O;
|
||||
wire [0:0] clb_cout;
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] direct_interc_10_out;
|
||||
wire [0:0] direct_interc_11_out;
|
||||
wire [0:0] direct_interc_12_out;
|
||||
wire [0:0] direct_interc_13_out;
|
||||
wire [0:0] direct_interc_14_out;
|
||||
wire [0:0] direct_interc_15_out;
|
||||
wire [0:0] direct_interc_16_out;
|
||||
wire [0:0] direct_interc_9_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_0_fle_cout;
|
||||
wire [0:1] logical_tile_clb_mode_default__fle_0_fle_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_1_fle_cout;
|
||||
wire [0:1] logical_tile_clb_mode_default__fle_1_fle_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_2_fle_cout;
|
||||
wire [0:1] logical_tile_clb_mode_default__fle_2_fle_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_3_fle_cout;
|
||||
wire [0:1] logical_tile_clb_mode_default__fle_3_fle_out;
|
||||
wire [0:0] mux_2level_size20_0_out;
|
||||
wire [0:9] mux_2level_size20_0_sram;
|
||||
wire [0:9] mux_2level_size20_0_sram_inv;
|
||||
wire [0:0] mux_2level_size20_10_out;
|
||||
wire [0:9] mux_2level_size20_10_sram;
|
||||
wire [0:9] mux_2level_size20_10_sram_inv;
|
||||
wire [0:0] mux_2level_size20_11_out;
|
||||
wire [0:9] mux_2level_size20_11_sram;
|
||||
wire [0:9] mux_2level_size20_11_sram_inv;
|
||||
wire [0:0] mux_2level_size20_12_out;
|
||||
wire [0:9] mux_2level_size20_12_sram;
|
||||
wire [0:9] mux_2level_size20_12_sram_inv;
|
||||
wire [0:0] mux_2level_size20_13_out;
|
||||
wire [0:9] mux_2level_size20_13_sram;
|
||||
wire [0:9] mux_2level_size20_13_sram_inv;
|
||||
wire [0:0] mux_2level_size20_14_out;
|
||||
wire [0:9] mux_2level_size20_14_sram;
|
||||
wire [0:9] mux_2level_size20_14_sram_inv;
|
||||
wire [0:0] mux_2level_size20_15_out;
|
||||
wire [0:9] mux_2level_size20_15_sram;
|
||||
wire [0:9] mux_2level_size20_15_sram_inv;
|
||||
wire [0:0] mux_2level_size20_1_out;
|
||||
wire [0:9] mux_2level_size20_1_sram;
|
||||
wire [0:9] mux_2level_size20_1_sram_inv;
|
||||
wire [0:0] mux_2level_size20_2_out;
|
||||
wire [0:9] mux_2level_size20_2_sram;
|
||||
wire [0:9] mux_2level_size20_2_sram_inv;
|
||||
wire [0:0] mux_2level_size20_3_out;
|
||||
wire [0:9] mux_2level_size20_3_sram;
|
||||
wire [0:9] mux_2level_size20_3_sram_inv;
|
||||
wire [0:0] mux_2level_size20_4_out;
|
||||
wire [0:9] mux_2level_size20_4_sram;
|
||||
wire [0:9] mux_2level_size20_4_sram_inv;
|
||||
wire [0:0] mux_2level_size20_5_out;
|
||||
wire [0:9] mux_2level_size20_5_sram;
|
||||
wire [0:9] mux_2level_size20_5_sram_inv;
|
||||
wire [0:0] mux_2level_size20_6_out;
|
||||
wire [0:9] mux_2level_size20_6_sram;
|
||||
wire [0:9] mux_2level_size20_6_sram_inv;
|
||||
wire [0:0] mux_2level_size20_7_out;
|
||||
wire [0:9] mux_2level_size20_7_sram;
|
||||
wire [0:9] mux_2level_size20_7_sram_inv;
|
||||
wire [0:0] mux_2level_size20_8_out;
|
||||
wire [0:9] mux_2level_size20_8_sram;
|
||||
wire [0:9] mux_2level_size20_8_sram_inv;
|
||||
wire [0:0] mux_2level_size20_9_out;
|
||||
wire [0:9] mux_2level_size20_9_sram;
|
||||
wire [0:9] mux_2level_size20_9_sram_inv;
|
||||
wire [0:0] mux_2level_size20_mem_0_ccff_tail;
|
||||
wire [0:0] mux_2level_size20_mem_10_ccff_tail;
|
||||
wire [0:0] mux_2level_size20_mem_11_ccff_tail;
|
||||
wire [0:0] mux_2level_size20_mem_12_ccff_tail;
|
||||
wire [0:0] mux_2level_size20_mem_13_ccff_tail;
|
||||
wire [0:0] mux_2level_size20_mem_14_ccff_tail;
|
||||
wire [0:0] mux_2level_size20_mem_1_ccff_tail;
|
||||
wire [0:0] mux_2level_size20_mem_2_ccff_tail;
|
||||
wire [0:0] mux_2level_size20_mem_3_ccff_tail;
|
||||
wire [0:0] mux_2level_size20_mem_4_ccff_tail;
|
||||
wire [0:0] mux_2level_size20_mem_5_ccff_tail;
|
||||
wire [0:0] mux_2level_size20_mem_6_ccff_tail;
|
||||
wire [0:0] mux_2level_size20_mem_7_ccff_tail;
|
||||
wire [0:0] mux_2level_size20_mem_8_ccff_tail;
|
||||
wire [0:0] mux_2level_size20_mem_9_ccff_tail;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.set(set),
|
||||
.reset(reset),
|
||||
.clk(clk),
|
||||
.fle_in({mux_2level_size20_0_out, mux_2level_size20_1_out, mux_2level_size20_2_out, mux_2level_size20_3_out}),
|
||||
.fle_cin(direct_interc_9_out),
|
||||
.fle_clk(direct_interc_10_out),
|
||||
.ccff_head(ccff_head),
|
||||
.fle_out(logical_tile_clb_mode_default__fle_0_fle_out[0:1]),
|
||||
.fle_cout(logical_tile_clb_mode_default__fle_0_fle_cout),
|
||||
.ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail));
|
||||
|
||||
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.set(set),
|
||||
.reset(reset),
|
||||
.clk(clk),
|
||||
.fle_in({mux_2level_size20_4_out, mux_2level_size20_5_out, mux_2level_size20_6_out, mux_2level_size20_7_out}),
|
||||
.fle_cin(direct_interc_11_out),
|
||||
.fle_clk(direct_interc_12_out),
|
||||
.ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail),
|
||||
.fle_out(logical_tile_clb_mode_default__fle_1_fle_out[0:1]),
|
||||
.fle_cout(logical_tile_clb_mode_default__fle_1_fle_cout),
|
||||
.ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail));
|
||||
|
||||
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.set(set),
|
||||
.reset(reset),
|
||||
.clk(clk),
|
||||
.fle_in({mux_2level_size20_8_out, mux_2level_size20_9_out, mux_2level_size20_10_out, mux_2level_size20_11_out}),
|
||||
.fle_cin(direct_interc_13_out),
|
||||
.fle_clk(direct_interc_14_out),
|
||||
.ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail),
|
||||
.fle_out(logical_tile_clb_mode_default__fle_2_fle_out[0:1]),
|
||||
.fle_cout(logical_tile_clb_mode_default__fle_2_fle_cout),
|
||||
.ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail));
|
||||
|
||||
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.set(set),
|
||||
.reset(reset),
|
||||
.clk(clk),
|
||||
.fle_in({mux_2level_size20_12_out, mux_2level_size20_13_out, mux_2level_size20_14_out, mux_2level_size20_15_out}),
|
||||
.fle_cin(direct_interc_15_out),
|
||||
.fle_clk(direct_interc_16_out),
|
||||
.ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail),
|
||||
.fle_out(logical_tile_clb_mode_default__fle_3_fle_out[0:1]),
|
||||
.fle_cout(logical_tile_clb_mode_default__fle_3_fle_cout),
|
||||
.ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail));
|
||||
|
||||
direct_interc direct_interc_0_ (
|
||||
.in(logical_tile_clb_mode_default__fle_0_fle_out[0]),
|
||||
.out(clb_O[0]));
|
||||
|
||||
direct_interc direct_interc_1_ (
|
||||
.in(logical_tile_clb_mode_default__fle_1_fle_out[0]),
|
||||
.out(clb_O[1]));
|
||||
|
||||
direct_interc direct_interc_2_ (
|
||||
.in(logical_tile_clb_mode_default__fle_2_fle_out[0]),
|
||||
.out(clb_O[2]));
|
||||
|
||||
direct_interc direct_interc_3_ (
|
||||
.in(logical_tile_clb_mode_default__fle_3_fle_out[0]),
|
||||
.out(clb_O[3]));
|
||||
|
||||
direct_interc direct_interc_4_ (
|
||||
.in(logical_tile_clb_mode_default__fle_0_fle_out[1]),
|
||||
.out(clb_O[4]));
|
||||
|
||||
direct_interc direct_interc_5_ (
|
||||
.in(logical_tile_clb_mode_default__fle_1_fle_out[1]),
|
||||
.out(clb_O[5]));
|
||||
|
||||
direct_interc direct_interc_6_ (
|
||||
.in(logical_tile_clb_mode_default__fle_2_fle_out[1]),
|
||||
.out(clb_O[6]));
|
||||
|
||||
direct_interc direct_interc_7_ (
|
||||
.in(logical_tile_clb_mode_default__fle_3_fle_out[1]),
|
||||
.out(clb_O[7]));
|
||||
|
||||
direct_interc direct_interc_8_ (
|
||||
.in(logical_tile_clb_mode_default__fle_3_fle_cout),
|
||||
.out(clb_cout));
|
||||
|
||||
direct_interc direct_interc_9_ (
|
||||
.in(clb_cin),
|
||||
.out(direct_interc_9_out));
|
||||
|
||||
direct_interc direct_interc_10_ (
|
||||
.in(clb_clk),
|
||||
.out(direct_interc_10_out));
|
||||
|
||||
direct_interc direct_interc_11_ (
|
||||
.in(logical_tile_clb_mode_default__fle_0_fle_cout),
|
||||
.out(direct_interc_11_out));
|
||||
|
||||
direct_interc direct_interc_12_ (
|
||||
.in(clb_clk),
|
||||
.out(direct_interc_12_out));
|
||||
|
||||
direct_interc direct_interc_13_ (
|
||||
.in(logical_tile_clb_mode_default__fle_1_fle_cout),
|
||||
.out(direct_interc_13_out));
|
||||
|
||||
direct_interc direct_interc_14_ (
|
||||
.in(clb_clk),
|
||||
.out(direct_interc_14_out));
|
||||
|
||||
direct_interc direct_interc_15_ (
|
||||
.in(logical_tile_clb_mode_default__fle_2_fle_cout),
|
||||
.out(direct_interc_15_out));
|
||||
|
||||
direct_interc direct_interc_16_ (
|
||||
.in(clb_clk),
|
||||
.out(direct_interc_16_out));
|
||||
|
||||
mux_2level_size20 mux_fle_0_in_0 (
|
||||
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
|
||||
.sram(mux_2level_size20_0_sram[0:9]),
|
||||
.sram_inv(mux_2level_size20_0_sram_inv[0:9]),
|
||||
.out(mux_2level_size20_0_out));
|
||||
|
||||
mux_2level_size20 mux_fle_0_in_1 (
|
||||
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
|
||||
.sram(mux_2level_size20_1_sram[0:9]),
|
||||
.sram_inv(mux_2level_size20_1_sram_inv[0:9]),
|
||||
.out(mux_2level_size20_1_out));
|
||||
|
||||
mux_2level_size20 mux_fle_0_in_2 (
|
||||
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
|
||||
.sram(mux_2level_size20_2_sram[0:9]),
|
||||
.sram_inv(mux_2level_size20_2_sram_inv[0:9]),
|
||||
.out(mux_2level_size20_2_out));
|
||||
|
||||
mux_2level_size20 mux_fle_0_in_3 (
|
||||
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
|
||||
.sram(mux_2level_size20_3_sram[0:9]),
|
||||
.sram_inv(mux_2level_size20_3_sram_inv[0:9]),
|
||||
.out(mux_2level_size20_3_out));
|
||||
|
||||
mux_2level_size20 mux_fle_1_in_0 (
|
||||
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
|
||||
.sram(mux_2level_size20_4_sram[0:9]),
|
||||
.sram_inv(mux_2level_size20_4_sram_inv[0:9]),
|
||||
.out(mux_2level_size20_4_out));
|
||||
|
||||
mux_2level_size20 mux_fle_1_in_1 (
|
||||
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
|
||||
.sram(mux_2level_size20_5_sram[0:9]),
|
||||
.sram_inv(mux_2level_size20_5_sram_inv[0:9]),
|
||||
.out(mux_2level_size20_5_out));
|
||||
|
||||
mux_2level_size20 mux_fle_1_in_2 (
|
||||
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
|
||||
.sram(mux_2level_size20_6_sram[0:9]),
|
||||
.sram_inv(mux_2level_size20_6_sram_inv[0:9]),
|
||||
.out(mux_2level_size20_6_out));
|
||||
|
||||
mux_2level_size20 mux_fle_1_in_3 (
|
||||
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
|
||||
.sram(mux_2level_size20_7_sram[0:9]),
|
||||
.sram_inv(mux_2level_size20_7_sram_inv[0:9]),
|
||||
.out(mux_2level_size20_7_out));
|
||||
|
||||
mux_2level_size20 mux_fle_2_in_0 (
|
||||
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
|
||||
.sram(mux_2level_size20_8_sram[0:9]),
|
||||
.sram_inv(mux_2level_size20_8_sram_inv[0:9]),
|
||||
.out(mux_2level_size20_8_out));
|
||||
|
||||
mux_2level_size20 mux_fle_2_in_1 (
|
||||
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
|
||||
.sram(mux_2level_size20_9_sram[0:9]),
|
||||
.sram_inv(mux_2level_size20_9_sram_inv[0:9]),
|
||||
.out(mux_2level_size20_9_out));
|
||||
|
||||
mux_2level_size20 mux_fle_2_in_2 (
|
||||
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
|
||||
.sram(mux_2level_size20_10_sram[0:9]),
|
||||
.sram_inv(mux_2level_size20_10_sram_inv[0:9]),
|
||||
.out(mux_2level_size20_10_out));
|
||||
|
||||
mux_2level_size20 mux_fle_2_in_3 (
|
||||
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
|
||||
.sram(mux_2level_size20_11_sram[0:9]),
|
||||
.sram_inv(mux_2level_size20_11_sram_inv[0:9]),
|
||||
.out(mux_2level_size20_11_out));
|
||||
|
||||
mux_2level_size20 mux_fle_3_in_0 (
|
||||
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
|
||||
.sram(mux_2level_size20_12_sram[0:9]),
|
||||
.sram_inv(mux_2level_size20_12_sram_inv[0:9]),
|
||||
.out(mux_2level_size20_12_out));
|
||||
|
||||
mux_2level_size20 mux_fle_3_in_1 (
|
||||
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
|
||||
.sram(mux_2level_size20_13_sram[0:9]),
|
||||
.sram_inv(mux_2level_size20_13_sram_inv[0:9]),
|
||||
.out(mux_2level_size20_13_out));
|
||||
|
||||
mux_2level_size20 mux_fle_3_in_2 (
|
||||
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
|
||||
.sram(mux_2level_size20_14_sram[0:9]),
|
||||
.sram_inv(mux_2level_size20_14_sram_inv[0:9]),
|
||||
.out(mux_2level_size20_14_out));
|
||||
|
||||
mux_2level_size20 mux_fle_3_in_3 (
|
||||
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
|
||||
.sram(mux_2level_size20_15_sram[0:9]),
|
||||
.sram_inv(mux_2level_size20_15_sram_inv[0:9]),
|
||||
.out(mux_2level_size20_15_out));
|
||||
|
||||
mux_2level_size20_mem mem_fle_0_in_0 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail),
|
||||
.ccff_tail(mux_2level_size20_mem_0_ccff_tail),
|
||||
.mem_out(mux_2level_size20_0_sram[0:9]),
|
||||
.mem_outb(mux_2level_size20_0_sram_inv[0:9]));
|
||||
|
||||
mux_2level_size20_mem mem_fle_0_in_1 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_2level_size20_mem_0_ccff_tail),
|
||||
.ccff_tail(mux_2level_size20_mem_1_ccff_tail),
|
||||
.mem_out(mux_2level_size20_1_sram[0:9]),
|
||||
.mem_outb(mux_2level_size20_1_sram_inv[0:9]));
|
||||
|
||||
mux_2level_size20_mem mem_fle_0_in_2 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_2level_size20_mem_1_ccff_tail),
|
||||
.ccff_tail(mux_2level_size20_mem_2_ccff_tail),
|
||||
.mem_out(mux_2level_size20_2_sram[0:9]),
|
||||
.mem_outb(mux_2level_size20_2_sram_inv[0:9]));
|
||||
|
||||
mux_2level_size20_mem mem_fle_0_in_3 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_2level_size20_mem_2_ccff_tail),
|
||||
.ccff_tail(mux_2level_size20_mem_3_ccff_tail),
|
||||
.mem_out(mux_2level_size20_3_sram[0:9]),
|
||||
.mem_outb(mux_2level_size20_3_sram_inv[0:9]));
|
||||
|
||||
mux_2level_size20_mem mem_fle_1_in_0 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_2level_size20_mem_3_ccff_tail),
|
||||
.ccff_tail(mux_2level_size20_mem_4_ccff_tail),
|
||||
.mem_out(mux_2level_size20_4_sram[0:9]),
|
||||
.mem_outb(mux_2level_size20_4_sram_inv[0:9]));
|
||||
|
||||
mux_2level_size20_mem mem_fle_1_in_1 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_2level_size20_mem_4_ccff_tail),
|
||||
.ccff_tail(mux_2level_size20_mem_5_ccff_tail),
|
||||
.mem_out(mux_2level_size20_5_sram[0:9]),
|
||||
.mem_outb(mux_2level_size20_5_sram_inv[0:9]));
|
||||
|
||||
mux_2level_size20_mem mem_fle_1_in_2 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_2level_size20_mem_5_ccff_tail),
|
||||
.ccff_tail(mux_2level_size20_mem_6_ccff_tail),
|
||||
.mem_out(mux_2level_size20_6_sram[0:9]),
|
||||
.mem_outb(mux_2level_size20_6_sram_inv[0:9]));
|
||||
|
||||
mux_2level_size20_mem mem_fle_1_in_3 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_2level_size20_mem_6_ccff_tail),
|
||||
.ccff_tail(mux_2level_size20_mem_7_ccff_tail),
|
||||
.mem_out(mux_2level_size20_7_sram[0:9]),
|
||||
.mem_outb(mux_2level_size20_7_sram_inv[0:9]));
|
||||
|
||||
mux_2level_size20_mem mem_fle_2_in_0 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_2level_size20_mem_7_ccff_tail),
|
||||
.ccff_tail(mux_2level_size20_mem_8_ccff_tail),
|
||||
.mem_out(mux_2level_size20_8_sram[0:9]),
|
||||
.mem_outb(mux_2level_size20_8_sram_inv[0:9]));
|
||||
|
||||
mux_2level_size20_mem mem_fle_2_in_1 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_2level_size20_mem_8_ccff_tail),
|
||||
.ccff_tail(mux_2level_size20_mem_9_ccff_tail),
|
||||
.mem_out(mux_2level_size20_9_sram[0:9]),
|
||||
.mem_outb(mux_2level_size20_9_sram_inv[0:9]));
|
||||
|
||||
mux_2level_size20_mem mem_fle_2_in_2 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_2level_size20_mem_9_ccff_tail),
|
||||
.ccff_tail(mux_2level_size20_mem_10_ccff_tail),
|
||||
.mem_out(mux_2level_size20_10_sram[0:9]),
|
||||
.mem_outb(mux_2level_size20_10_sram_inv[0:9]));
|
||||
|
||||
mux_2level_size20_mem mem_fle_2_in_3 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_2level_size20_mem_10_ccff_tail),
|
||||
.ccff_tail(mux_2level_size20_mem_11_ccff_tail),
|
||||
.mem_out(mux_2level_size20_11_sram[0:9]),
|
||||
.mem_outb(mux_2level_size20_11_sram_inv[0:9]));
|
||||
|
||||
mux_2level_size20_mem mem_fle_3_in_0 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_2level_size20_mem_11_ccff_tail),
|
||||
.ccff_tail(mux_2level_size20_mem_12_ccff_tail),
|
||||
.mem_out(mux_2level_size20_12_sram[0:9]),
|
||||
.mem_outb(mux_2level_size20_12_sram_inv[0:9]));
|
||||
|
||||
mux_2level_size20_mem mem_fle_3_in_1 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_2level_size20_mem_12_ccff_tail),
|
||||
.ccff_tail(mux_2level_size20_mem_13_ccff_tail),
|
||||
.mem_out(mux_2level_size20_13_sram[0:9]),
|
||||
.mem_outb(mux_2level_size20_13_sram_inv[0:9]));
|
||||
|
||||
mux_2level_size20_mem mem_fle_3_in_2 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_2level_size20_mem_13_ccff_tail),
|
||||
.ccff_tail(mux_2level_size20_mem_14_ccff_tail),
|
||||
.mem_out(mux_2level_size20_14_sram[0:9]),
|
||||
.mem_outb(mux_2level_size20_14_sram_inv[0:9]));
|
||||
|
||||
mux_2level_size20_mem mem_fle_3_in_3 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_2level_size20_mem_14_ccff_tail),
|
||||
.ccff_tail(ccff_tail),
|
||||
.mem_out(mux_2level_size20_15_sram[0:9]),
|
||||
.mem_outb(mux_2level_size20_15_sram_inv[0:9]));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for logical_tile_clb_mode_clb_ -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
// ----- END Physical programmable logic block Verilog module: clb -----
|
||||
|
|
@ -0,0 +1,137 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for pb_type: fle
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ----- BEGIN Physical programmable logic block Verilog module: fle -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for logical_tile_clb_mode_default__fle -----
|
||||
module logical_tile_clb_mode_default__fle(pReset,
|
||||
prog_clk,
|
||||
set,
|
||||
reset,
|
||||
clk,
|
||||
fle_in,
|
||||
fle_cin,
|
||||
fle_clk,
|
||||
ccff_head,
|
||||
fle_out,
|
||||
fle_cout,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] pReset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] set;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] reset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:3] fle_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] fle_cin;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] fle_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:1] fle_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] fle_cout;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
wire [0:3] fle_in;
|
||||
wire [0:0] fle_cin;
|
||||
wire [0:0] fle_clk;
|
||||
wire [0:1] fle_out;
|
||||
wire [0:0] fle_cout;
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] direct_interc_3_out;
|
||||
wire [0:0] direct_interc_4_out;
|
||||
wire [0:0] direct_interc_5_out;
|
||||
wire [0:0] direct_interc_6_out;
|
||||
wire [0:0] direct_interc_7_out;
|
||||
wire [0:0] direct_interc_8_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout;
|
||||
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.set(set),
|
||||
.reset(reset),
|
||||
.clk(clk),
|
||||
.fabric_in({direct_interc_3_out, direct_interc_4_out, direct_interc_5_out, direct_interc_6_out}),
|
||||
.fabric_cin(direct_interc_7_out),
|
||||
.fabric_clk(direct_interc_8_out),
|
||||
.ccff_head(ccff_head),
|
||||
.fabric_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0:1]),
|
||||
.fabric_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout),
|
||||
.ccff_tail(ccff_tail));
|
||||
|
||||
direct_interc direct_interc_0_ (
|
||||
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0]),
|
||||
.out(fle_out[0]));
|
||||
|
||||
direct_interc direct_interc_1_ (
|
||||
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[1]),
|
||||
.out(fle_out[1]));
|
||||
|
||||
direct_interc direct_interc_2_ (
|
||||
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout),
|
||||
.out(fle_cout));
|
||||
|
||||
direct_interc direct_interc_3_ (
|
||||
.in(fle_in[0]),
|
||||
.out(direct_interc_3_out));
|
||||
|
||||
direct_interc direct_interc_4_ (
|
||||
.in(fle_in[1]),
|
||||
.out(direct_interc_4_out));
|
||||
|
||||
direct_interc direct_interc_5_ (
|
||||
.in(fle_in[2]),
|
||||
.out(direct_interc_5_out));
|
||||
|
||||
direct_interc direct_interc_6_ (
|
||||
.in(fle_in[3]),
|
||||
.out(direct_interc_6_out));
|
||||
|
||||
direct_interc direct_interc_7_ (
|
||||
.in(fle_cin),
|
||||
.out(direct_interc_7_out));
|
||||
|
||||
direct_interc direct_interc_8_ (
|
||||
.in(fle_clk),
|
||||
.out(direct_interc_8_out));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for logical_tile_clb_mode_default__fle -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
// ----- END Physical programmable logic block Verilog module: fle -----
|
||||
|
|
@ -0,0 +1,234 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for pb_type: fabric
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ----- BEGIN Physical programmable logic block Verilog module: fabric -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric -----
|
||||
module logical_tile_clb_mode_default__fle_mode_physical__fabric(pReset,
|
||||
prog_clk,
|
||||
set,
|
||||
reset,
|
||||
clk,
|
||||
fabric_in,
|
||||
fabric_cin,
|
||||
fabric_clk,
|
||||
ccff_head,
|
||||
fabric_out,
|
||||
fabric_cout,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] pReset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] set;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] reset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:3] fabric_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] fabric_cin;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] fabric_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:1] fabric_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] fabric_cout;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
wire [0:3] fabric_in;
|
||||
wire [0:0] fabric_cin;
|
||||
wire [0:0] fabric_clk;
|
||||
wire [0:1] fabric_out;
|
||||
wire [0:0] fabric_cout;
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] direct_interc_1_out;
|
||||
wire [0:0] direct_interc_2_out;
|
||||
wire [0:0] direct_interc_3_out;
|
||||
wire [0:0] direct_interc_4_out;
|
||||
wire [0:0] direct_interc_5_out;
|
||||
wire [0:0] direct_interc_6_out;
|
||||
wire [0:0] direct_interc_7_out;
|
||||
wire [0:0] direct_interc_8_out;
|
||||
wire [0:0] direct_interc_9_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0_adder_cout;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0_adder_sumout;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail;
|
||||
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out;
|
||||
wire [0:0] mux_1level_tapbuf_size2_0_out;
|
||||
wire [0:2] mux_1level_tapbuf_size2_0_sram;
|
||||
wire [0:2] mux_1level_tapbuf_size2_0_sram_inv;
|
||||
wire [0:0] mux_1level_tapbuf_size2_1_out;
|
||||
wire [0:2] mux_1level_tapbuf_size2_1_sram;
|
||||
wire [0:2] mux_1level_tapbuf_size2_1_sram_inv;
|
||||
wire [0:0] mux_1level_tapbuf_size2_mem_0_ccff_tail;
|
||||
wire [0:3] mux_1level_tapbuf_size3_0_sram;
|
||||
wire [0:3] mux_1level_tapbuf_size3_0_sram_inv;
|
||||
wire [0:3] mux_1level_tapbuf_size3_1_sram;
|
||||
wire [0:3] mux_1level_tapbuf_size3_1_sram_inv;
|
||||
wire [0:0] mux_1level_tapbuf_size3_mem_0_ccff_tail;
|
||||
wire [0:0] mux_1level_tapbuf_size3_mem_1_ccff_tail;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.frac_logic_in({direct_interc_1_out, direct_interc_2_out, direct_interc_3_out, direct_interc_4_out}),
|
||||
.ccff_head(ccff_head),
|
||||
.frac_logic_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0:1]),
|
||||
.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail));
|
||||
|
||||
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
|
||||
.set(set),
|
||||
.reset(reset),
|
||||
.clk(clk),
|
||||
.ff_D(mux_1level_tapbuf_size2_0_out),
|
||||
.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q),
|
||||
.ff_clk(direct_interc_5_out));
|
||||
|
||||
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
|
||||
.set(set),
|
||||
.reset(reset),
|
||||
.clk(clk),
|
||||
.ff_D(mux_1level_tapbuf_size2_1_out),
|
||||
.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q),
|
||||
.ff_clk(direct_interc_6_out));
|
||||
|
||||
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0 (
|
||||
.adder_a(direct_interc_7_out),
|
||||
.adder_b(direct_interc_8_out),
|
||||
.adder_cin(direct_interc_9_out),
|
||||
.adder_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0_adder_cout),
|
||||
.adder_sumout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0_adder_sumout));
|
||||
|
||||
mux_1level_tapbuf_size3 mux_fabric_out_0 (
|
||||
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0_adder_cout, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]}),
|
||||
.sram(mux_1level_tapbuf_size3_0_sram[0:3]),
|
||||
.sram_inv(mux_1level_tapbuf_size3_0_sram_inv[0:3]),
|
||||
.out(fabric_out[0]));
|
||||
|
||||
mux_1level_tapbuf_size3 mux_fabric_out_1 (
|
||||
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0_adder_sumout, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]}),
|
||||
.sram(mux_1level_tapbuf_size3_1_sram[0:3]),
|
||||
.sram_inv(mux_1level_tapbuf_size3_1_sram_inv[0:3]),
|
||||
.out(fabric_out[1]));
|
||||
|
||||
mux_1level_tapbuf_size3_mem mem_fabric_out_0 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail),
|
||||
.ccff_tail(mux_1level_tapbuf_size3_mem_0_ccff_tail),
|
||||
.mem_out(mux_1level_tapbuf_size3_0_sram[0:3]),
|
||||
.mem_outb(mux_1level_tapbuf_size3_0_sram_inv[0:3]));
|
||||
|
||||
mux_1level_tapbuf_size3_mem mem_fabric_out_1 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_1level_tapbuf_size3_mem_0_ccff_tail),
|
||||
.ccff_tail(mux_1level_tapbuf_size3_mem_1_ccff_tail),
|
||||
.mem_out(mux_1level_tapbuf_size3_1_sram[0:3]),
|
||||
.mem_outb(mux_1level_tapbuf_size3_1_sram_inv[0:3]));
|
||||
|
||||
direct_interc direct_interc_0_ (
|
||||
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0_adder_cout),
|
||||
.out(fabric_cout));
|
||||
|
||||
direct_interc direct_interc_1_ (
|
||||
.in(fabric_in[0]),
|
||||
.out(direct_interc_1_out));
|
||||
|
||||
direct_interc direct_interc_2_ (
|
||||
.in(fabric_in[1]),
|
||||
.out(direct_interc_2_out));
|
||||
|
||||
direct_interc direct_interc_3_ (
|
||||
.in(fabric_in[2]),
|
||||
.out(direct_interc_3_out));
|
||||
|
||||
direct_interc direct_interc_4_ (
|
||||
.in(fabric_in[3]),
|
||||
.out(direct_interc_4_out));
|
||||
|
||||
direct_interc direct_interc_5_ (
|
||||
.in(fabric_clk),
|
||||
.out(direct_interc_5_out));
|
||||
|
||||
direct_interc direct_interc_6_ (
|
||||
.in(fabric_clk),
|
||||
.out(direct_interc_6_out));
|
||||
|
||||
direct_interc direct_interc_7_ (
|
||||
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]),
|
||||
.out(direct_interc_7_out));
|
||||
|
||||
direct_interc direct_interc_8_ (
|
||||
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]),
|
||||
.out(direct_interc_8_out));
|
||||
|
||||
direct_interc direct_interc_9_ (
|
||||
.in(fabric_cin),
|
||||
.out(direct_interc_9_out));
|
||||
|
||||
mux_1level_tapbuf_size2 mux_ff_0_D_0 (
|
||||
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0_adder_cout}),
|
||||
.sram(mux_1level_tapbuf_size2_0_sram[0:2]),
|
||||
.sram_inv(mux_1level_tapbuf_size2_0_sram_inv[0:2]),
|
||||
.out(mux_1level_tapbuf_size2_0_out));
|
||||
|
||||
mux_1level_tapbuf_size2 mux_ff_1_D_0 (
|
||||
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0_adder_sumout}),
|
||||
.sram(mux_1level_tapbuf_size2_1_sram[0:2]),
|
||||
.sram_inv(mux_1level_tapbuf_size2_1_sram_inv[0:2]),
|
||||
.out(mux_1level_tapbuf_size2_1_out));
|
||||
|
||||
mux_1level_tapbuf_size2_mem mem_ff_0_D_0 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_1level_tapbuf_size3_mem_1_ccff_tail),
|
||||
.ccff_tail(mux_1level_tapbuf_size2_mem_0_ccff_tail),
|
||||
.mem_out(mux_1level_tapbuf_size2_0_sram[0:2]),
|
||||
.mem_outb(mux_1level_tapbuf_size2_0_sram_inv[0:2]));
|
||||
|
||||
mux_1level_tapbuf_size2_mem mem_ff_1_D_0 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(mux_1level_tapbuf_size2_mem_0_ccff_tail),
|
||||
.ccff_tail(ccff_tail),
|
||||
.mem_out(mux_1level_tapbuf_size2_1_sram[0:2]),
|
||||
.mem_outb(mux_1level_tapbuf_size2_1_sram_inv[0:2]));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
// ----- END Physical programmable logic block Verilog module: fabric -----
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for primitive pb_type: adder
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder -----
|
||||
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder(adder_a,
|
||||
adder_b,
|
||||
adder_cin,
|
||||
adder_cout,
|
||||
adder_sumout);
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] adder_a;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] adder_b;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] adder_cin;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] adder_cout;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] adder_sumout;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
wire [0:0] adder_a;
|
||||
wire [0:0] adder_b;
|
||||
wire [0:0] adder_cin;
|
||||
wire [0:0] adder_cout;
|
||||
wire [0:0] adder_sumout;
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
ADDF ADDF_0_ (
|
||||
.A(adder_a),
|
||||
.B(adder_b),
|
||||
.CI(adder_cin),
|
||||
.SUM(adder_sumout),
|
||||
.CO(adder_cout));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for primitive pb_type: ff
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff -----
|
||||
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff(set,
|
||||
reset,
|
||||
clk,
|
||||
ff_D,
|
||||
ff_Q,
|
||||
ff_clk);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] set;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] reset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ff_D;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ff_Q;
|
||||
//----- CLOCK PORTS -----
|
||||
input [0:0] ff_clk;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
wire [0:0] ff_D;
|
||||
wire [0:0] ff_Q;
|
||||
wire [0:0] ff_clk;
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
DFFSRQ DFFSRQ_0_ (
|
||||
.SET(set),
|
||||
.RST(reset),
|
||||
.CK(clk),
|
||||
.D(ff_D),
|
||||
.Q(ff_Q));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for pb_type: frac_logic
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ----- BEGIN Physical programmable logic block Verilog module: frac_logic -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic -----
|
||||
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic(pReset,
|
||||
prog_clk,
|
||||
frac_logic_in,
|
||||
ccff_head,
|
||||
frac_logic_out,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] pReset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:3] frac_logic_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:1] frac_logic_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
wire [0:3] frac_logic_in;
|
||||
wire [0:1] frac_logic_out;
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] direct_interc_1_out;
|
||||
wire [0:0] direct_interc_2_out;
|
||||
wire [0:0] direct_interc_3_out;
|
||||
wire [0:0] direct_interc_4_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail;
|
||||
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out;
|
||||
wire [0:2] mux_1level_tapbuf_size2_0_sram;
|
||||
wire [0:2] mux_1level_tapbuf_size2_0_sram_inv;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.frac_lut4_in({direct_interc_1_out, direct_interc_2_out, direct_interc_3_out, direct_interc_4_out}),
|
||||
.ccff_head(ccff_head),
|
||||
.frac_lut4_lut3_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0:1]),
|
||||
.frac_lut4_lut4_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out),
|
||||
.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail));
|
||||
|
||||
mux_1level_tapbuf_size2 mux_frac_logic_out_0 (
|
||||
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]}),
|
||||
.sram(mux_1level_tapbuf_size2_0_sram[0:2]),
|
||||
.sram_inv(mux_1level_tapbuf_size2_0_sram_inv[0:2]),
|
||||
.out(frac_logic_out[0]));
|
||||
|
||||
mux_1level_tapbuf_size2_mem mem_frac_logic_out_0 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail),
|
||||
.ccff_tail(ccff_tail),
|
||||
.mem_out(mux_1level_tapbuf_size2_0_sram[0:2]),
|
||||
.mem_outb(mux_1level_tapbuf_size2_0_sram_inv[0:2]));
|
||||
|
||||
direct_interc direct_interc_0_ (
|
||||
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[1]),
|
||||
.out(frac_logic_out[1]));
|
||||
|
||||
direct_interc direct_interc_1_ (
|
||||
.in(frac_logic_in[0]),
|
||||
.out(direct_interc_1_out));
|
||||
|
||||
direct_interc direct_interc_2_ (
|
||||
.in(frac_logic_in[1]),
|
||||
.out(direct_interc_2_out));
|
||||
|
||||
direct_interc direct_interc_3_ (
|
||||
.in(frac_logic_in[2]),
|
||||
.out(direct_interc_3_out));
|
||||
|
||||
direct_interc direct_interc_4_ (
|
||||
.in(frac_logic_in[3]),
|
||||
.out(direct_interc_4_out));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
// ----- END Physical programmable logic block Verilog module: frac_logic -----
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for primitive pb_type: frac_lut4
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 -----
|
||||
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4(pReset,
|
||||
prog_clk,
|
||||
frac_lut4_in,
|
||||
ccff_head,
|
||||
frac_lut4_lut3_out,
|
||||
frac_lut4_lut4_out,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] pReset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:3] frac_lut4_in;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:1] frac_lut4_lut3_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] frac_lut4_lut4_out;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
wire [0:3] frac_lut4_in;
|
||||
wire [0:1] frac_lut4_lut3_out;
|
||||
wire [0:0] frac_lut4_lut4_out;
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] frac_lut4_0_mode;
|
||||
wire [0:0] frac_lut4_0_mode_inv;
|
||||
wire [0:15] frac_lut4_0_sram;
|
||||
wire [0:15] frac_lut4_0_sram_inv;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
frac_lut4 frac_lut4_0_ (
|
||||
.in(frac_lut4_in[0:3]),
|
||||
.sram(frac_lut4_0_sram[0:15]),
|
||||
.sram_inv(frac_lut4_0_sram_inv[0:15]),
|
||||
.mode(frac_lut4_0_mode),
|
||||
.mode_inv(frac_lut4_0_mode_inv),
|
||||
.lut3_out(frac_lut4_lut3_out[0:1]),
|
||||
.lut4_out(frac_lut4_lut4_out));
|
||||
|
||||
frac_lut4_DFFR_mem frac_lut4_DFFR_mem (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(ccff_head),
|
||||
.ccff_tail(ccff_tail),
|
||||
.mem_out({frac_lut4_0_sram[0:15], frac_lut4_0_mode}),
|
||||
.mem_outb({frac_lut4_0_sram_inv[0:15], frac_lut4_0_mode_inv}));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for pb_type: io
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ----- BEGIN Physical programmable logic block Verilog module: io -----
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for logical_tile_io_mode_io_ -----
|
||||
module logical_tile_io_mode_io_(pReset,
|
||||
prog_clk,
|
||||
gfpga_pad_GPIO_PAD,
|
||||
io_outpad,
|
||||
ccff_head,
|
||||
io_inpad,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] pReset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- GPIO PORTS -----
|
||||
inout [0:0] gfpga_pad_GPIO_PAD;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] io_outpad;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] io_inpad;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
wire [0:0] io_outpad;
|
||||
wire [0:0] io_inpad;
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] direct_interc_1_out;
|
||||
wire [0:0] logical_tile_io_mode_physical__iopad_0_iopad_inpad;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD),
|
||||
.iopad_outpad(direct_interc_1_out),
|
||||
.ccff_head(ccff_head),
|
||||
.iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad),
|
||||
.ccff_tail(ccff_tail));
|
||||
|
||||
direct_interc direct_interc_0_ (
|
||||
.in(logical_tile_io_mode_physical__iopad_0_iopad_inpad),
|
||||
.out(io_inpad));
|
||||
|
||||
direct_interc direct_interc_1_ (
|
||||
.in(io_outpad),
|
||||
.out(direct_interc_1_out));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for logical_tile_io_mode_io_ -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
// ----- END Physical programmable logic block Verilog module: io -----
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Verilog modules for primitive pb_type: iopad
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
// ----- Verilog module for logical_tile_io_mode_physical__iopad -----
|
||||
module logical_tile_io_mode_physical__iopad(pReset,
|
||||
prog_clk,
|
||||
gfpga_pad_GPIO_PAD,
|
||||
iopad_outpad,
|
||||
ccff_head,
|
||||
iopad_inpad,
|
||||
ccff_tail);
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] pReset;
|
||||
//----- GLOBAL PORTS -----
|
||||
input [0:0] prog_clk;
|
||||
//----- GPIO PORTS -----
|
||||
inout [0:0] gfpga_pad_GPIO_PAD;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] iopad_outpad;
|
||||
//----- INPUT PORTS -----
|
||||
input [0:0] ccff_head;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] iopad_inpad;
|
||||
//----- OUTPUT PORTS -----
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//----- BEGIN wire-connection ports -----
|
||||
wire [0:0] iopad_outpad;
|
||||
wire [0:0] iopad_inpad;
|
||||
//----- END wire-connection ports -----
|
||||
|
||||
|
||||
//----- BEGIN Registered ports -----
|
||||
//----- END Registered ports -----
|
||||
|
||||
|
||||
wire [0:0] GPIO_0_DIR;
|
||||
wire [0:0] GPIO_DFFR_mem_undriven_mem_outb;
|
||||
|
||||
// ----- BEGIN Local short connections -----
|
||||
// ----- END Local short connections -----
|
||||
// ----- BEGIN Local output short connections -----
|
||||
// ----- END Local output short connections -----
|
||||
|
||||
GPIO GPIO_0_ (
|
||||
.PAD(gfpga_pad_GPIO_PAD),
|
||||
.A(iopad_outpad),
|
||||
.DIR(GPIO_0_DIR),
|
||||
.Y(iopad_inpad));
|
||||
|
||||
GPIO_DFFR_mem GPIO_DFFR_mem (
|
||||
.pReset(pReset),
|
||||
.prog_clk(prog_clk),
|
||||
.ccff_head(ccff_head),
|
||||
.ccff_tail(ccff_tail),
|
||||
.mem_out(GPIO_0_DIR),
|
||||
.mem_outb(GPIO_DFFR_mem_undriven_mem_outb));
|
||||
|
||||
endmodule
|
||||
// ----- END Verilog module for logical_tile_io_mode_physical__iopad -----
|
||||
|
||||
//----- Default net type -----
|
||||
`default_nettype none
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,334 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_clb_ in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[10] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[11] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[10] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[11] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[10] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[11] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[10] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[11] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_cin[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_cin[0] 1.599999994e-10
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[10] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[11] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[10] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[11] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[10] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[11] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[10] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[11] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[10] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[11] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[10] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[11] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[10] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[11] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[10] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[11] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[10] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[11] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[10] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[11] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[10] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[11] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[10] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[11] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 7.499999927e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 7.499999927e-11
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_cout[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[0] 4.500000025e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_sumout[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[1] 2.500000033e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[1] 4.500000025e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[1] 2.500000033e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_cout[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 4.500000025e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0/adder_sumout[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 4.500000025e-11
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue