tangxifan
|
26e4db56ad
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[Test] Add new test case for the native fracturable LUT4
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2020-11-25 22:21:23 -07:00 |
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tangxifan
|
17070c6405
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[Doc] Update README in openfpga arch directory for native fracturable LUT design
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2020-11-25 22:19:20 -07:00 |
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tangxifan
|
f6a667de58
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[Arch] Add openfpga architecture using native fracturable LUT
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2020-11-25 22:18:03 -07:00 |
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tangxifan
|
eda671592e
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[Doc] Update README about new keyword about fracturable LUT
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2020-11-25 22:12:56 -07:00 |
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tangxifan
|
0f841aa6d1
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[Arch] Add an example architecture using native fracturable LUT
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2020-11-25 22:11:14 -07:00 |
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tangxifan
|
fd80cacaa3
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[Flow] Add example script for behaviorial verilog generation
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2020-11-22 21:14:10 -07:00 |
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tangxifan
|
617f7e3062
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[Flow] disable signal initialization for behavioral verilog generation
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2020-11-22 21:13:22 -07:00 |
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tangxifan
|
5eb04e6fff
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[HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals
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2020-11-22 20:53:32 -07:00 |
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tangxifan
|
655da9f3d0
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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tangxifan
|
348872f8a4
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[Flow] Adapt OpenFPGA shell script for the preprocessing flag option changes
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2020-11-22 16:12:28 -07:00 |
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tangxifan
|
845436fa71
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[Test] Add sequential benchmark for global tile clock test case
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2020-11-17 14:34:54 -07:00 |
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tangxifan
|
91b0dbbaa2
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[Script] Add example openfpga shell run script when using global tile clocks
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2020-11-17 14:33:12 -07:00 |
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tangxifan
|
485258a9ea
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[Test] Add test case for global clock from tiles
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2020-11-10 19:24:25 -07:00 |
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tangxifan
|
f29916921a
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[Arch] Add openfpga arch for using global clocks from tiles
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2020-11-10 19:20:08 -07:00 |
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tangxifan
|
a6531d9e8d
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[Arch] Add k4 arch using global clock from tile port (with zero fc)
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2020-11-10 19:17:34 -07:00 |
|
tangxifan
|
75ce4b5e25
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[Arch] Fine tune example arch
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2020-11-10 14:38:47 -07:00 |
|
tangxifan
|
d127304760
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[Arch] Update sample arch using local clock from physical tile ports
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2020-11-10 14:31:58 -07:00 |
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tangxifan
|
4ca2a129c2
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[Arch] Add an sample architecture where global clock port is defined from tile ports
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2020-11-10 11:47:03 -07:00 |
|
tangxifan
|
70734abc35
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[Arch] Remove QN from stdcell arch
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2020-11-06 11:20:13 -07:00 |
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tangxifan
|
1a79a55646
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[HDL] Add DFF cell with reset but only 1 output
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2020-11-06 11:19:19 -07:00 |
|
tangxifan
|
2aab8bf910
|
[Arch] Use single-output DFF for a standard cell FPGA
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2020-11-06 10:26:39 -07:00 |
|
tangxifan
|
7d46b35296
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[HDL] Add single-output DFF HDL
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2020-11-06 10:18:37 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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55f7a2c187
|
Merge pull request #116 from LNIS-Projects/dev
Extended I/O Support for SoC I/O interface
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2020-11-04 21:55:37 -07:00 |
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tangxifan
|
bce8233019
|
[Arch] Bug fix in caravel arch
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2020-11-04 20:58:58 -07:00 |
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tangxifan
|
6b48ee7f0b
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[Test] Add new test for caravel io support
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2020-11-04 20:58:40 -07:00 |
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tangxifan
|
c85edb4738
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[Arch] Bug fix for embedded io arch
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2020-11-04 20:52:47 -07:00 |
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tangxifan
|
a6c7bb2c48
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[Arch] Update OpenFPGA arch for new syntax on I/O
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2020-11-04 20:24:02 -07:00 |
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tangxifan
|
dd86f7f464
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[Arch] Path architecture for caravel i/o interface
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2020-11-04 17:16:21 -07:00 |
|
tangxifan
|
c074e88dcd
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[HDL] Add embedded I/O HDL for Caravel SoC interface
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2020-11-04 17:09:59 -07:00 |
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tangxifan
|
aebf7453d0
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[Arch] Add architecture files with compatible I/O capacity with caravel SoC
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2020-11-04 16:57:00 -07:00 |
|
tangxifan
|
61376a2979
|
[Test] Add test cases for various tile organization
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2020-11-04 16:32:52 -07:00 |
|
tangxifan
|
cf455df555
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[Arch] Add architecture for bottom-right and top-left tile organization
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2020-11-04 16:24:36 -07:00 |
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tangxifan
|
46ca406f10
|
[Arch] Add a new vpr architecture with new tile organization
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2020-11-04 16:20:01 -07:00 |
|
tangxifan
|
049ca14461
|
[Doc] Add new naming rules for vpr architecture files
|
2020-11-04 16:17:56 -07:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
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5d41cc6d23
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Merge pull request #114 from LNIS-Projects/dev
Support I/O interfaces for Embedded FPGAs
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2020-11-02 21:10:52 -07:00 |
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tangxifan
|
c036c87d6d
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[HDL] Bug fix in the GP output pad
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2020-11-02 18:37:53 -07:00 |
|
tangxifan
|
3b49e6d090
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[Arch] Patch embedded IO architecture by forcing only 1 pad per block
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2020-11-02 15:39:31 -07:00 |
|
tangxifan
|
c512644a09
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[Arch] Patch embedded I/O example architecture
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2020-11-02 15:16:19 -07:00 |
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tangxifan
|
7e9e0ec9d4
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[HDL] Bug fix in I/O HDL code
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2020-11-02 15:15:45 -07:00 |
|
tangxifan
|
2f237a6240
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[HDL] Add HDL codes for embedded I/Os
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2020-11-02 14:01:27 -07:00 |
|
tangxifan
|
55b77ac6cb
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[Arch] Bug fixed in embedded FPGA architecture
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2020-11-02 13:57:15 -07:00 |
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tangxifan
|
a7e7fa2005
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[Arch] Update arch with true embedded I/O definition
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2020-11-02 13:29:40 -07:00 |
|
tangxifan
|
65ca53ac98
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[Test] Update test case with the new arch name
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2020-11-02 13:16:42 -07:00 |
|
tangxifan
|
8c8190047f
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[Arch] Rename architecture files for embedded I/Os
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2020-11-02 13:15:19 -07:00 |
|
tangxifan
|
bc00dee858
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[Test] Add test case for embedded I/O
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2020-11-02 12:28:25 -07:00 |
|
tangxifan
|
f86f43d287
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[Arch] Add openfpga architecture file for constrained pin equivalence
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2020-11-02 12:27:40 -07:00 |
|
tangxifan
|
795b30f76b
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[Arch] Add VPR architecture with partial pin equivalence
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2020-11-02 11:54:25 -07:00 |
|
tangxifan
|
032cbfb8b2
|
Merge pull request #113 from LNIS-Projects/dev
Multi-region support on Frame-based Configuration Protocol
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2020-10-31 10:37:38 -06:00 |
|
tangxifan
|
4c14428400
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[Test] Add test case for fast configuration support on multi-region frame-based configuration protocol
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2020-10-30 10:50:00 -06:00 |
|
tangxifan
|
ca7d43275d
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[Test] Add test case for multi_region configuration frame
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2020-10-30 10:48:29 -06:00 |