tangxifan
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ca867ea6fa
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add power gate inverter test case (full testbench)
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2020-07-22 20:09:52 -06:00 |
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tangxifan
|
1a1c3885e7
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use k6 n10 in mux designs to speed up CI
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2020-07-22 13:54:09 -06:00 |
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tangxifan
|
95c1fe61e1
|
use k6 n8 in mux design to speed up CI
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2020-07-22 13:49:03 -06:00 |
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tangxifan
|
f754c8af06
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use k6_n10 architecture to reduce CI runtime
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2020-07-22 13:45:55 -06:00 |
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tangxifan
|
92c3449999
|
bug fix in the regression test due to benchmark changes
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2020-07-22 13:17:05 -06:00 |
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tangxifan
|
05dccadf21
|
bug fix in the testcases using yosys_vpr flow
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2020-07-22 12:44:19 -06:00 |
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tangxifan
|
1d36de817f
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adapt generate bitstream testcase to use yosys vpr flow
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2020-07-22 12:24:34 -06:00 |
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tangxifan
|
b96cdbf857
|
adapt preconfig test cases to use yosys_vpr flow
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2020-07-22 12:23:39 -06:00 |
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tangxifan
|
d8804f4ec1
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deploy yosys_vpr flow to basic regression tests
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2020-07-22 12:21:59 -06:00 |
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tangxifan
|
eb070694b5
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fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture
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2020-07-15 17:52:41 -06:00 |
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tangxifan
|
ca90f337a7
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add fast configuration chain test case
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2020-07-15 11:56:47 -06:00 |
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tangxifan
|
1e6955aaa4
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rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |
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tangxifan
|
f9a2bb0490
|
Reorganize task directory
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2020-07-04 19:06:41 -06:00 |
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tangxifan
|
4f8260a7ba
|
remove obselete codes and update regression tests
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2020-07-04 17:31:34 -06:00 |
|
tangxifan
|
1c634e4600
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add missing task file for generate bitstream test case
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2020-07-02 17:24:51 -06:00 |
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tangxifan
|
0d81f60fd8
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add new options to openfpga task configuration files
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2020-06-12 19:48:39 -06:00 |
ganeshgore
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559564c333
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2020-06-12 17:31:14 -06:00 |
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tangxifan
|
2d35848cfa
|
add external key test cases
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2020-06-12 13:11:21 -06:00 |
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tangxifan
|
65b387a589
|
develop test cases for fabric keys
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2020-06-12 11:32:52 -06:00 |
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tangxifan
|
068d9943e7
|
update all the templates and regression test cases with simulation settings
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2020-06-11 19:31:16 -06:00 |
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tangxifan
|
1842bf51e1
|
deploy read_openfpga_simulation_setting in CI on a single test case
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2020-06-11 19:31:16 -06:00 |
|
tangxifan
|
c87dbc4880
|
start using counter benchmark in regression tests
|
2020-06-11 19:31:15 -06:00 |
|
tangxifan
|
3f9afea3e8
|
add preconfig testbench test case for memory bank configuration protocol
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
288294c23a
|
add fast configuration test case for memory bank configuration protocol
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
73d4c835b7
|
add regression test case for memory bank
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2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
2def059b5b
|
add standalone configuration protocol to pre config test cases
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
5f6a790eff
|
add new test cases for the standalone memory configuration protocol
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
a5138113e4
|
add fast configuration testcase
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
8b3e79766c
|
add fast configuration option to fpga_verilog to speed up full testbench simulation
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
05aa166a9e
|
add preconfig testbench cases to regression tests for different configuration protocols
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
827e2e6713
|
file moving in regression tests
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
1e73fd6def
|
create configuration frame example script
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
3a0d3b4e95
|
fix the broken CI/regression tests due to incorrect file path
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
3fa3b17061
|
start testing the frame-based configuration protocol. To distinguish, rename xml to identify between configuration chain and frame-based. This should not impact the pre-config testbenches.
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
fc2b09514e
|
add configuration chain write to regression tests
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
98fbcb5410
|
add time unit test for SDC generation to CI
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
4083fae41a
|
add new test cases about user-defined simulation settings
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
889bc8dbe8
|
add more test cases about LUT design and deploy to CI
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
889f179ce7
|
add local encoder test case
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
98a658a013
|
bug fixed in routing_test.v. Deployed to regression tests
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
6dd8d347e1
|
try to deploy microbenchmark test_mode_low but fail due to .v port mismatch with .blif
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
42cede37fa
|
add testcases on generate fabric/testbench only
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
9bf91bd92a
|
start testing mcnc_big20 using OpenFPGA tasks
|
2020-06-11 19:30:55 -06:00 |
|
ganeshgore
|
c31b20dc91
|
Added support for simulation setting file in the task flow
|
2020-06-11 19:28:13 -06:00 |
|
ganeshgore
|
c1b73efa62
|
Added support for simulation setting file in the task flow
|
2020-06-10 23:12:30 -06:00 |
|
tangxifan
|
90f608baea
|
changing task mcnc file for debugging (temporarily now) Will be corrected later
|
2020-04-23 18:58:39 -06:00 |
|
tangxifan
|
f9fcc6b471
|
tweak mcnc scripts by stop VRP to remove buffers. Now passed mcnc big20 in Verilog/Bitstream generation
|
2020-04-22 18:24:09 -06:00 |
|
tangxifan
|
726185cd5e
|
add test cases using spypad architecture
|
2020-04-22 12:56:57 -06:00 |
|
tangxifan
|
9761d13eef
|
update microbenchmark and2 module name
|
2020-04-20 13:37:39 -06:00 |
|
tangxifan
|
489ca75230
|
adapt benchmark and_latch module name to be different than benchmark and
|
2020-04-20 13:15:05 -06:00 |