tangxifan
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6d6295ef93
|
Add test cases about using standard cell mux2
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2020-04-07 11:12:47 -06:00 |
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tangxifan
|
d39d7a68ce
|
add test cases for using tree-like multiplexer
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2020-04-07 10:46:49 -06:00 |
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tangxifan
|
92a3a444f9
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update VPR7 to support global I/O ports
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2020-04-06 20:44:00 -06:00 |
|
Xifan Tang
|
7a4137fdcf
|
doc update for packable XML syntax in VPR
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2020-04-06 18:37:05 -06:00 |
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tangxifan
|
13cd48c119
|
add support on packable/unpackable modes in VPR architecture
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2020-04-06 16:07:49 -06:00 |
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tangxifan
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7e89c2c65f
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2020-04-06 14:10:38 -06:00 |
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tangxifan
|
6eb125ec2a
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Now cross-column/row is optional to direct annotation in OpenFPGA architecture XML
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2020-04-06 14:09:52 -06:00 |
ganeshgore
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87c25a6084
|
Added GCC paths to source
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2020-04-06 00:35:28 -06:00 |
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ganeshgore
|
e1db4df744
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Created task for FPGA shell run
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2020-04-06 00:35:07 -06:00 |
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ganeshgore
|
ea4122a8a4
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Updated openfpga_flow and task file to support sheel run
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2020-04-06 00:34:36 -06:00 |
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ganeshgore
|
7f98ecc8a6
|
OpenFPGA shell run test script template
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2020-04-06 00:32:43 -06:00 |
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ganeshgore
|
eb3b02277a
|
Added XML and benchmarks for testing
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2020-04-06 00:32:06 -06:00 |
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ganeshgore
|
77f7e13ba7
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2020-04-05 20:59:10 -06:00 |
|
Xifan Tang
|
1a3a748dd2
|
update documentation with the support on spypads and global I/O ports
|
2020-04-05 20:12:28 -06:00 |
|
tangxifan
|
3369d724e9
|
bug fixing in Verilog top-level testbench generation
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2020-04-05 17:50:11 -06:00 |
|
tangxifan
|
decc1dc4b2
|
debugged global gp input/output port support
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2020-04-05 17:39:30 -06:00 |
|
tangxifan
|
bcb86801fa
|
bug fixed in gpio naming for module manager ports
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2020-04-05 17:26:44 -06:00 |
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tangxifan
|
5f4e7dc5d4
|
support gpinput and gpoutput ports in module manager and circuit library
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2020-04-05 16:52:21 -06:00 |
|
tangxifan
|
bc47b3ca94
|
update verilog module writer to the global spy ports
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2020-04-05 16:04:13 -06:00 |
|
tangxifan
|
8b583b7917
|
debugging spy port builder in module manager
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2020-04-05 16:01:25 -06:00 |
|
tangxifan
|
ca45efd13d
|
add testing script for the spy io
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2020-04-05 15:24:40 -06:00 |
|
tangxifan
|
3b63ad6657
|
add test openfpga arch XML with spy pad
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2020-04-05 15:23:07 -06:00 |
|
tangxifan
|
836f722f20
|
start supporting global output ports in module manager
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2020-04-05 15:19:46 -06:00 |
|
ganeshgore
|
d1d3446568
|
backedup partial upgrade for fpga_flow script
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2020-04-05 11:36:24 -06:00 |
|
tangxifan
|
32c74ad811
|
added FPGA architecture with I/Os on the left and right sides
|
2020-04-01 15:46:38 -06:00 |
|
Xifan Tang
|
6ce0fe4ef2
|
doc update for FPGA-bitstream to better motivate the different types of bitstream
|
2020-04-01 12:57:28 -06:00 |
|
Xifan Tang
|
fd8248d9dd
|
update documentation: the addon syntax on VPR and configuration protocols
|
2020-04-01 12:35:52 -06:00 |
|
tangxifan
|
63306ce3a0
|
add comments to explain the memory organization in the top-level module
|
2020-04-01 11:05:30 -06:00 |
|
tangxifan
|
5d12f499f0
|
hotfix on undriven pins on the connection blocks
|
2020-03-29 16:26:23 -06:00 |
|
tangxifan
|
07e1979498
|
add architecture examples on wide memory blocks (width=2). tileable routing is working
|
2020-03-28 15:41:26 -06:00 |
|
tangxifan
|
ff9cc50527
|
relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads
|
2020-03-27 20:09:50 -06:00 |
|
tangxifan
|
e601a648cc
|
relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
|
2020-03-27 19:07:34 -06:00 |
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tangxifan
|
34a1b61ecb
|
add an example FPGA architecture with AIB interface at the right side of I/Os
|
2020-03-27 18:45:27 -06:00 |
|
tangxifan
|
4bf0a63ae6
|
bug fixed for multiple io types defined in FPGA architectures
|
2020-03-27 16:32:15 -06:00 |
|
tangxifan
|
7c9c2451f2
|
debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
|
2020-03-27 16:03:42 -06:00 |
|
tangxifan
|
b09b051249
|
add all the test cases considering tileable, carry chain, direct connection and memory blocks
|
2020-03-27 13:58:35 -06:00 |
|
tangxifan
|
78964ce71c
|
update documentation on the through channel
|
2020-03-27 11:34:39 -06:00 |
|
tangxifan
|
e47a0a4422
|
add through channel architecture example
|
2020-03-27 11:32:44 -06:00 |
|
tangxifan
|
5ce078fe60
|
minor fix on rr_graph.clear()
|
2020-03-27 11:26:14 -06:00 |
|
tangxifan
|
91a618466d
|
bug fixing for rr_graph.clear() function
|
2020-03-27 10:52:48 -06:00 |
|
tangxifan
|
3b3c39454b
|
update print_route() in VPR to show correct track_id when tileable routing is used
|
2020-03-25 17:55:28 -06:00 |
|
Xifan Tang
|
b4221e94bb
|
add documentation on the tileable routing and thru channel support
|
2020-03-25 16:52:42 -06:00 |
|
Xifan Tang
|
cb6afea07c
|
update documentation on a new option in FPGA-SDC to constrain zero-delay paths
|
2020-03-25 16:00:25 -06:00 |
|
tangxifan
|
329b0a9cf1
|
add options to enable SDC constraints on zero-delay paths
|
2020-03-25 15:55:30 -06:00 |
|
Xifan Tang
|
3a74fb7a04
|
update documentation for the new options
|
2020-03-25 15:23:21 -06:00 |
|
tangxifan
|
4a0128f240
|
minor fix on the SDC format
|
2020-03-25 14:46:31 -06:00 |
|
tangxifan
|
62b6de8437
|
update the SDC of VPR7+OpenFPGA to be even with VPR8+OpenFPGA
|
2020-03-25 14:44:42 -06:00 |
|
tangxifan
|
c2e5d6b8e2
|
add options to dsiable SDC for non-clock global ports
|
2020-03-25 14:38:13 -06:00 |
|
tangxifan
|
787dc8ce83
|
added ASCII OpenFPGA logo in shell interface
|
2020-03-25 11:16:04 -06:00 |
|
tangxifan
|
b6bdf78d95
|
bug fixed for heterogeneous block instances in top module
|
2020-03-24 17:39:26 -06:00 |