Christophe Alexandre
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c3dd704bf3
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Fixing typo in run_fpga_flow.py
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2021-10-18 09:13:42 +00:00 |
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Christophe Alexandre
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d411967159
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Fixing small typo in run_fpga_flow.py
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2021-10-15 10:01:12 +00:00 |
tangxifan
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698fc43de5
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Merge pull request #28 from RapidSilicon/update_from_upstream
Update from upstream
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2021-10-14 21:09:35 -07:00 |
nadeemyaseen-rs
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0f10cc4c81
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change the path in ci_test.sh
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2021-10-14 19:43:37 +05:00 |
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nadeemyaseen-rs
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e0cfd46ec7
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Merge remote-tracking branch 'upstream/master' into update_from_upstream
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2021-10-14 19:25:31 +05:00 |
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tangxifan
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c8ffc34125
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Merge pull request #26 from RapidSilicon/qlbank_multibank_sr
Now QuickLogic Memory Bank Support Multiple Shift Register Chains in each Configuration Region
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2021-10-11 11:38:31 -07:00 |
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tangxifan
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b2c4e3314e
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[Test] Bug fix in test cases
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2021-10-11 10:28:09 -07:00 |
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tangxifan
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8566e2a0cd
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[Test] Renaming test case to follow naming convention as other fabric key test cases
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2021-10-11 09:56:23 -07:00 |
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tangxifan
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2bf203cd00
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[Test] Deploy the new test to basic regression test
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2021-10-11 09:54:39 -07:00 |
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tangxifan
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b8b02d37d5
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[Test] Added a new test case to validate the correctness of custom shift register chain through fabric key file
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2021-10-11 09:53:23 -07:00 |
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tangxifan
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cdcb07256b
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[Arch] Add an example fabric key that models a shift-register-based QuickLogic memory bank using custom chain organization
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2021-10-11 09:49:22 -07:00 |
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tangxifan
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6586ea7816
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[Engine] Bug fix for fabric key writer which errors out when there is no BL/WL banks in the architecture
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2021-10-11 09:40:02 -07:00 |
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Christophe Alexandre
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1017a6a619
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Fixing small typo in openfpga.sh
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2021-10-11 13:52:31 +00:00 |
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tangxifan
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982a324e0d
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[Test] Temporarily disable some tests; Will go back later
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2021-10-10 23:30:50 -07:00 |
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tangxifan
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546350ae41
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[FPGA-Verilog] Revert back to the previous precomputing strategy for shift register clocks
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2021-10-10 23:19:39 -07:00 |
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tangxifan
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40fd89fdb4
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[arch] Update fabric key for multi-region
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2021-10-10 22:03:49 -07:00 |
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tangxifan
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b9c540ec3f
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[Engine] Upgrade fabric key writer to support BL/WL shift register banks
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2021-10-10 21:14:14 -07:00 |
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tangxifan
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202b50c0e3
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[FPGA-Verilog] Fixed a weird bug which causes totally different results in fixed and auto shift register clock freq; However, this is a dirty fix. Require further study to know why
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2021-10-10 20:57:23 -07:00 |
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tangxifan
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4e2df9d69c
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[Lib] Bug fix in unintialized memory in fabric key
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2021-10-10 17:59:11 -07:00 |
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tangxifan
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57159fc121
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[Doc] Update documentation for the new syntax in configuration protocol and fabric key file format
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2021-10-10 17:46:45 -07:00 |
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tangxifan
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de3275e9ba
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[FPGA-Verilog] Fixed a critical in verilog testbench which caused the last bit of bitstream skipped when loading to shift register chains
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2021-10-10 16:56:07 -07:00 |
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tangxifan
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1c46a92559
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[FPGA-Bitstream] Bug fix
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2021-10-09 21:59:56 -07:00 |
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tangxifan
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6aa4991314
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[FPGA-Verilog] Bug fix
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2021-10-09 21:34:07 -07:00 |
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tangxifan
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7810f376c8
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[FPGA-Bitstream] Patch code comments
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2021-10-09 21:03:01 -07:00 |
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tangxifan
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8f9e564cd5
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[Test] Add the new test to basic regression test
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2021-10-09 20:45:23 -07:00 |
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tangxifan
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6122863548
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[Test] Add a test case to validate the multi-shift-register-chain QL memory bank
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2021-10-09 20:44:28 -07:00 |
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tangxifan
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82e77b42c5
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[Arch] Add an example architecture which uses multiple shift register chain for a single-ql-bank FPGA
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2021-10-09 20:43:55 -07:00 |
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tangxifan
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34575f7222
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[FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank
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2021-10-09 20:39:45 -07:00 |
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tangxifan
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aac74d9163
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[Engine] Bug fix
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2021-10-09 18:46:20 -07:00 |
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tangxifan
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fa08f44107
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[Engine] Bug fix
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2021-10-09 16:58:56 -07:00 |
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tangxifan
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19a551e641
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[Engine] Upgrade fabric generator to support multiple shift register banks in a configuration region
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2021-10-09 16:44:04 -07:00 |
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tangxifan
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932beb480a
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[Engine] Add fast look-up to the shift register bank data structure
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2021-10-08 22:00:01 -07:00 |
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tangxifan
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e3ff40d9e0
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[Engine] Add missing return value
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2021-10-08 20:17:55 -07:00 |
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tangxifan
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39a69e0d88
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[Engine] Upgrading fabric generator to support customizable shift register banks from fabric key and configuration protocols
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2021-10-08 17:58:06 -07:00 |
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tangxifan
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8f5f30792f
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[Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface
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2021-10-08 15:25:37 -07:00 |
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tangxifan
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f7484d4323
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[Engine] Update the key memory data structure to contain shift register bank general information
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2021-10-08 10:42:18 -07:00 |
ganeshgore
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d85e55aef2
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Merge pull request #385 from coolbreeze413/add-wget-to-dependencies
add wget to list of dependencies
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2021-10-07 21:04:29 -06:00 |
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tangxifan
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92eebd9abb
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[Lib] Upgrade fabric key writer to support the BL/WL shift register banks
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2021-10-07 17:05:35 -07:00 |
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tangxifan
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eddafb42c8
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[Lib] Upgrade parser for fabric key to support shift register banks
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2021-10-07 15:38:42 -07:00 |
coolbreeze413
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f60f5b4ae5
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add wget to list of dependencies
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2021-10-08 03:22:30 +05:30 |
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tangxifan
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a15798a4e1
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[Lib] Upgrade fabric key data structure to support shift register bank definitions
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2021-10-07 14:42:21 -07:00 |
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tangxifan
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75bd579474
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Merge pull request #25 from RapidSilicon/qlbank_sr
Now dont' care bits are truelly seen in single-chain and flatten QuickLogic memory bank
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2021-10-07 13:28:36 -07:00 |
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tangxifan
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9693a269ee
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[FPGA-Bitstream] Now dont' care bits are truelly seen in single-chain and flatten QuickLogic memory bank
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2021-10-07 11:31:16 -07:00 |
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tangxifan
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a464625101
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Merge pull request #24 from RapidSilicon/qlbank_sr
Support custom shift register clock frequency through the simulation setting file
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2021-10-06 17:53:22 -07:00 |
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tangxifan
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54a8809b3c
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[FPGA-Verilog] Bug fix in computing clock frequency for shift register chains
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2021-10-06 16:49:28 -07:00 |
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tangxifan
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8aa2647878
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[Script] Bug fix in slow clock frequency in shift register chain contraints
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2021-10-06 16:49:01 -07:00 |
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tangxifan
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40b589dc6d
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[Doc] Update documentation about the clock definition for programming clocks in simulation settings
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2021-10-06 13:50:33 -07:00 |
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tangxifan
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27153bbc89
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[FPGA-Verilog] Bug fix in matching shift register clocks between verilog ports and simulation setting definition
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2021-10-06 13:38:51 -07:00 |
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tangxifan
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dc5aedc393
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[Script] Correct naming for clocks in shifter register chain defined in simulation setting files
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2021-10-06 13:36:35 -07:00 |
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tangxifan
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a1eaacf5a8
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[Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency
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2021-10-06 12:12:15 -07:00 |