tangxifan
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071757dc52
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add module nets to connect grids and sbs
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2019-10-15 16:08:51 -06:00 |
Baudouin Chauviere
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33e50bbc8c
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fix
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2019-10-01 16:54:16 -06:00 |
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tangxifan
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d7ac7d3649
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start refactoring the switch block verilog generation
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2019-09-17 20:40:26 -06:00 |
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tangxifan
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d83cad7c2e
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refactoring Verilog generation for routing channels
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2019-09-16 17:35:51 -06:00 |
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Baudouin Chauviere
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737cfb1086
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Correction to the explicit Verilog for FPGAs above 2x2
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2019-09-13 16:02:06 -06:00 |
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Baudouin Chauviere
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8f5ad2eb67
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Snapshot of progress
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2019-07-02 10:10:48 -06:00 |
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Baudouin Chauviere
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0e04b88c8f
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Include new files in the parameter spreading
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2019-07-01 11:27:48 -06:00 |
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Baudouin Chauviere
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7c742f1cbb
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Stable, is_explicit propagated through the code. Not implemented though except for muxes
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2019-06-27 10:29:57 -06:00 |
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Baudouin Chauviere
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0ce9846e47
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Stable, unfinished
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2019-06-26 16:54:41 -06:00 |
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tangxifan
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d50fb7ee19
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fixed the bug in determine passing wires for rr_gsb
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2019-06-26 10:50:23 -06:00 |
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tangxifan
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8a8f4153ce
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use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB
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2019-06-10 12:50:10 -06:00 |
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tangxifan
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17bc7fc296
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update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
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2019-06-08 20:11:22 -06:00 |
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tangxifan
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2c46da6888
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clean-up warnings Verilog routing generator
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2019-05-24 16:29:17 -06:00 |
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tangxifan
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be4643b8a6
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updated Verilog generator to use compact CBs and SBs. SPICE generator to be updated
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2019-05-10 10:21:06 -06:00 |
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tangxifan
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46d44fa42a
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |