Baudouin Chauviere
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0ce9846e47
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Stable, unfinished
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2019-06-26 16:54:41 -06:00 |
tangxifan
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59df305668
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bug fixing and reorganize rr_graph builder source files
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2019-06-23 16:40:13 -06:00 |
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tangxifan
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548242b368
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plug-in tileable rr generator which can be enable by a XML property
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2019-06-20 21:06:26 -06:00 |
AurelienUoU
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ff00e4c79c
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Free only if it's possible to free
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2019-06-19 16:15:30 -06:00 |
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tangxifan
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44d21ebb90
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fixed a bug in Verilog generator supporting SRAM5T
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2019-06-13 14:42:39 -06:00 |
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tangxifan
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ca363da30c
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add options to specify output directory of SB XML
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2019-05-28 15:19:10 -06:00 |
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Baudouin Chauviere
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b48a27acf0
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-13 14:45:57 -06:00 |
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Baudouin Chauviere
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2019840d7c
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cleaned unused variables
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2019-05-13 14:45:02 -06:00 |
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tangxifan
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a3c3f2b892
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developing compact routing hierarchy
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2019-05-08 20:49:21 -06:00 |
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AurelienUoU
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42f20eda60
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Add the user matching for internal register in formal verification script generation
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2019-05-03 10:24:02 -06:00 |
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tangxifan
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46d44fa42a
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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tangxifan
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72fbd8d6a8
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update blif reader to identify clock signals
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2018-12-10 13:28:44 -07:00 |
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Aur??Lien ALACCHI
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0580d8243f
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Add Autochek testbench option
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2018-12-08 17:19:12 -07:00 |
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Baudouin Chauviere
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b6bb419e1d
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add a ModelSim option
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2018-12-06 14:13:37 -07:00 |
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Aur??Lien ALACCHI
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9a8c7b391a
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Add process for modelsim script autogeneration
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2018-12-05 09:20:47 -07:00 |
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Aur??Lien ALACCHI
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8ac566ecc0
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Add timing and initialization for simulation
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2018-12-04 17:32:09 -07:00 |
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tangxifan
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c67ba5f58a
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clean up codes
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2018-09-27 14:26:08 -06:00 |
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tangxifan
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d683134b12
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rename customized vpr7 to vpr7 XML to Production
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2018-09-17 23:10:45 -06:00 |