tangxifan
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aa070b2a41
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further clean-up sample arch.xml
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2020-01-17 09:38:35 -07:00 |
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tangxifan
|
910c69d7e5
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clean up and reorganize XML about technology library
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2020-01-17 09:24:58 -07:00 |
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tangxifan
|
5c69f57559
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sample_arch:move cmos/rram variation to technology library XML nodes
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2020-01-16 20:58:45 -07:00 |
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tangxifan
|
95edd3c091
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clean up the sample arch
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2020-01-16 20:52:47 -07:00 |
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tangxifan
|
a598929fe7
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add circuit library checker in the test
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2020-01-16 20:25:00 -07:00 |
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tangxifan
|
f7a7c56366
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move OpenFPGAArch to openfpga namespace
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2020-01-16 20:22:56 -07:00 |
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tangxifan
|
d6adfa0821
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add XML parsing for delay matrix and wire parasitics for circuit library
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2020-01-16 20:14:39 -07:00 |
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tangxifan
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2e0ce78054
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add XML writing for buffers in circuit library
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2020-01-16 17:21:41 -07:00 |
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tangxifan
|
9ba42cd540
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add XML writer for circuit ports
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2020-01-16 16:05:11 -07:00 |
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tangxifan
|
0304d723c0
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add XML writer for design technology of a circuit model
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2020-01-16 14:45:41 -07:00 |
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tangxifan
|
3ace7f8ef7
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move generic data structures to openfpgautil library
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2020-01-16 13:26:55 -07:00 |
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tangxifan
|
d232391250
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developed XML writer for circuit library and start porting functions to openfpgautil library
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2020-01-16 12:32:29 -07:00 |
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tangxifan
|
e282f813bc
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rename circuit settings to openfpga arch and update sample architecture
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2020-01-15 20:28:04 -07:00 |
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tangxifan
|
264dc8458d
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add XML parsing for delay matrix in circuit model
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2020-01-15 20:21:53 -07:00 |
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tangxifan
|
602d0bde4c
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add XML parsing for wire parasitics in circuit model
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2020-01-15 19:54:57 -07:00 |
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tangxifan
|
999c364b25
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added XML parsing for circuit model ports
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2020-01-15 17:29:49 -07:00 |
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tangxifan
|
c20e1d48d2
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added XML parsing for pass-gate-logic in circuit models
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2020-01-15 15:49:02 -07:00 |
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tangxifan
|
a9b122d584
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add XML parsing for buffer models in circuit library
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2020-01-15 15:27:49 -07:00 |
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tangxifan
|
35d6c9661b
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Finish the first version of XML parser for design technology of circuit models
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2020-01-14 16:24:27 -07:00 |
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tangxifan
|
5937ffc809
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add XML parsing for buffer/pass-gate-logic -related properties
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2020-01-14 15:44:24 -07:00 |
|
tangxifan
|
56113e1aab
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adding XML parsing for design tech of circuit model
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2020-01-14 14:10:00 -07:00 |
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tangxifan
|
2692d0fc35
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adding XML parsing for SPICE and Verilog netlist for each circuit model
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2020-01-14 08:45:27 -07:00 |
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tangxifan
|
82d83ddceb
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reorganized the read XML openfpga arch
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2020-01-14 08:33:48 -07:00 |
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tangxifan
|
ca3ca14cc7
|
fixed bugs in XML when parsing circuit model types
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2020-01-13 21:52:13 -07:00 |
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tangxifan
|
db503ffebf
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add openfpga read xml executable and start min unit test
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2020-01-13 21:05:58 -07:00 |
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tangxifan
|
d6c69ea7c6
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developing XML parser for circuit model name and type
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2020-01-12 23:45:51 -07:00 |
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tangxifan
|
e2f641fdb3
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add example architecture for openfpga and developing XML parser
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2020-01-12 22:39:38 -07:00 |
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tangxifan
|
2e986608ba
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initial commit on parser for reading openfpga arch xml
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2020-01-12 21:33:28 -07:00 |
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tangxifan
|
5dea648be6
|
add missing CMakeList for libarchopenfpga
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2020-01-12 18:15:36 -07:00 |
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tangxifan
|
48ecb6e48b
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immigrate XML parser for circuit_lib to library readarchopenfpga
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2020-01-12 18:11:00 -07:00 |