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master

5c8a59f447 · Merge pull request #1897 from lnis-uofu/patch_update · Updated 2024-11-13 23:36:24 -06:00
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Branches

tangxifan-patch-1

1e5afb985c · Update contact.rst · Updated 2021-11-30 22:25:15 -06:00
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yosys+verific_support

a707226ba6 · Added 'basic_tests/verific_test' test case into regression tests suite. · Updated 2021-11-01 08:33:33 -05:00
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ys_hq

8a8d434057 · [Github] Debugging · Updated 2021-10-29 16:10:28 -05:00
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gg_ci

5e912b3c51 · Merge pull request #392 from lnis-uofu/gg_ci_cd_dev · Updated 2021-10-19 10:33:38 -05:00
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yosys_plugin_support

d6ee683601 · add prefix for yosys for plugin Makefile to find, add yosys-config path to plugin Makefile invocation · Updated 2021-10-13 18:16:53 -05:00
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yosys_plugin_support_clone

84111430be · Restored yosys paths · Updated 2021-10-08 01:37:54 -05:00
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kkumar23-patch-4

1088968116 · replace opt_rmdff · Updated 2021-09-23 08:34:04 -05:00
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kkumar23-patch-3

099335170a · replace opt_rmdff · Updated 2021-09-23 08:31:53 -05:00
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kkumar23-patch-2

3016c64bda · replace opt_rmdff · Updated 2021-09-23 08:29:37 -05:00
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kkumar23-patch-1

5fdf81b6fa · Update qlf_yosys.ys · Updated 2021-09-23 08:24:55 -05:00
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timing_annotation

0783072be7 · fixed errors · Updated 2021-08-16 17:12:51 -05:00
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revert-366-accept_absolute_task_paths

68aef15c2f · Revert "Accept absolute project paths in the 'run_fpga_task.py' script" · Updated 2021-08-13 13:15:53 -05:00
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bram_changes

c5808594b9 · added processor task run · Updated 2021-07-20 13:57:11 -05:00
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verilog_testbench

b7356d23aa · Merge branch 'master' into verilog_testbench · Updated 2021-07-01 22:11:12 -05:00
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opt_signal_init

67dec810eb · [Tool] Remove icarus simulator flag; Reduce the file size of preconfigured fabric wrapper by only output the necessary force/deposit HDL codes · Updated 2021-06-24 18:27:32 -05:00
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yosys_update

e7a245c2c4 · Merge branch 'master' into yosys_update · Updated 2021-06-23 11:40:07 -05:00
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partial_reconfiguration

3c9c089e64 · Merge pull request #307 from lnis-uofu/io_map_file · Updated 2021-04-27 18:19:07 -05:00
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yosys_as_env_var

3e5ebc3dc3 · Updating qlf_yosys.tcl file with correct condition to pick .so · Updated 2021-04-19 07:55:10 -05:00
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dff_techmap

0b49c22682 · [Tool] Now Verilog testbench generator support adding dedicated stimuli for reset signals from benchmarks · Updated 2021-04-18 17:11:11 -05:00
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power_estimation

80e2070ca4 · activity file name fix · Updated 2021-04-06 10:29:16 -05:00
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