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activity file name fix

This commit is contained in:
Andrew Pond 2021-04-06 09:29:16 -06:00
parent 391b606265
commit 80e2070ca4
2 changed files with 3 additions and 2 deletions
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4
openfpga_flow/misc/fpgaflow_default_tool_path.conf
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@ -50,8 +50,8 @@ yosys_out_blif=${PATH:TOP_MODULE}_yosys_out.blif
yosys_output=yosys_output.txt
# ACE2 and intermidiate file
activity_file=${PATH:TOP_MODULE}_ace_out.act
ace_output_blif=${PATH:TOP_MODULE}_ace_out.blif
activity_file=${PATH:TOP_MODULE}.act
ace_output_blif=${PATH:TOP_MODULE}.blif
corrected_format_blif=${PATH:TOP_MODULE}.blif
blackbox_blif=${PATH:TOP_MODULE}_bb.blif

1
openfpga_flow/scripts/run_fpga_flow.py
View File

@ -634,6 +634,7 @@ def run_openfpga_shell():
path_variables["OPENFPGA_ARCH_FILE"] = args.openfpga_arch_file
path_variables["VPR_TESTBENCH_BLIF"] = args.top_module+".blif"
path_variables["ACTIVITY_FILE"] = args.top_module+"_ace_out.act"
path_variables["TECH_PROPERTIES"] = args.power_tech
path_variables["REFERENCE_VERILOG_TESTBENCH"] = args.top_module + \
"_output_verilog.v"