2019-04-10 02:24:37 -05:00
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#!/bin/bash
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set -e
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2019-08-31 23:36:18 -05:00
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start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
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2020-06-11 13:05:12 -05:00
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cd ${TRAVIS_BUILD_DIR}
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2019-12-30 15:06:20 -06:00
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2020-04-12 13:57:13 -05:00
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###############################################
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# OpenFPGA Shell with VPR8
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##############################################
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2020-07-27 18:05:46 -05:00
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echo -e "FPGA-Verilog Feature Tests";
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2020-05-04 13:36:06 -05:00
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2020-05-01 16:05:59 -05:00
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echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks";
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2020-07-27 18:18:59 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/single_mode --debug --show_thread_logs
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2020-04-20 14:16:52 -05:00
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2020-09-21 18:38:16 -05:00
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echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 ";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs
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2020-10-10 21:29:00 -05:00
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echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 using AND gate to switch modes";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4_and_switch --debug --show_thread_logs
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2020-05-01 16:05:59 -05:00
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echo -e "Testing Verilog generation for LUTs: simple fracturable LUT6 ";
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2020-09-21 18:38:16 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut6 --debug --show_thread_logs
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2020-05-01 16:05:59 -05:00
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echo -e "Testing Verilog generation for LUTs: LUT6 with intermediate buffers";
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2020-07-27 18:18:59 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/intermediate_buffer --debug --show_thread_logs
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2020-04-12 13:57:13 -05:00
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2020-04-12 15:08:24 -05:00
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echo -e "Testing Verilog generation with VPR's untileable routing architecture ";
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2020-07-27 18:18:59 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/untileable --debug --show_thread_logs
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2020-04-12 15:08:24 -05:00
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2020-04-12 15:27:05 -05:00
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echo -e "Testing Verilog generation with hard adder chain in CLBs ";
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2020-07-27 18:18:59 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/hard_adder --debug --show_thread_logs
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2020-04-12 15:27:05 -05:00
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echo -e "Testing Verilog generation with 16k block RAMs ";
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2020-07-27 18:18:59 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/dpram16k --debug --show_thread_logs
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2020-04-12 15:27:05 -05:00
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2020-04-12 15:37:08 -05:00
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echo -e "Testing Verilog generation with 16k block RAMs spanning two columns ";
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2020-07-27 18:18:59 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/wide_dpram16k --debug --show_thread_logs
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2020-04-12 15:37:08 -05:00
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2020-04-12 16:01:47 -05:00
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echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA ";
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2020-07-27 18:18:59 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/multi_io_capacity --debug --show_thread_logs
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2020-04-12 16:01:47 -05:00
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echo -e "Testing Verilog generation with I/Os only on left and right sides of an FPGA ";
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2020-07-27 18:18:59 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/reduced_io --debug --show_thread_logs
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2020-04-12 16:01:47 -05:00
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2020-04-12 16:43:19 -05:00
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echo -e "Testing Verilog generation with adder chain across an FPGA";
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2020-07-27 18:18:59 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/adder_chain --debug --show_thread_logs
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2020-04-12 16:43:19 -05:00
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2020-04-12 16:28:22 -05:00
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echo -e "Testing Verilog generation with shift register chain across an FPGA";
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2020-07-27 18:18:59 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/register_chain --debug --show_thread_logs
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2020-04-12 16:28:22 -05:00
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echo -e "Testing Verilog generation with scan chain across an FPGA";
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2020-07-27 18:18:59 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/scan_chain --debug --show_thread_logs
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2020-04-12 16:28:22 -05:00
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2020-07-27 18:05:46 -05:00
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echo -e "Testing Verilog generation with routing multiplexers implemented by tree structure";
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2020-07-27 18:18:59 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/tree_structure --debug --show_thread_logs
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2020-04-12 16:39:45 -05:00
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2020-07-27 18:05:46 -05:00
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echo -e "Testing Verilog generation with routing multiplexers implemented by standard cell MUX2";
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2020-07-27 18:18:59 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/stdcell_mux2 --debug --show_thread_logs
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2020-04-12 16:39:45 -05:00
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2020-07-27 18:05:46 -05:00
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echo -e "Testing Verilog generation with routing multiplexers implemented by local encoders";
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2020-07-27 18:18:59 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/local_encoder --debug --show_thread_logs
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2020-05-01 15:56:07 -05:00
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2020-09-14 16:48:08 -05:00
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echo -e "Testing Verilog generation with routing multiplexers without buffers";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/debuf_mux --debug --show_thread_logs
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2020-09-14 17:11:48 -05:00
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echo -e "Testing Verilog generation with routing multiplexers with input buffers only";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs
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2020-09-14 17:16:03 -05:00
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echo -e "Testing Verilog generation with routing multiplexers with output buffers only";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/outbuf_only_mux --debug --show_thread_logs
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2020-10-13 12:40:49 -05:00
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echo -e "Testing Verilog generation with routing multiplexers with constant gnd input";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/const_input_gnd --debug --show_thread_logs
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2020-10-13 13:04:07 -05:00
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echo -e "Testing Verilog generation with routing multiplexers without constant inputs";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/no_const_input --debug --show_thread_logs
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2020-04-12 20:55:47 -05:00
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echo -e "Testing Verilog generation with behavioral description";
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2020-07-27 18:18:59 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs
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2020-04-12 20:55:47 -05:00
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2020-04-12 21:00:20 -05:00
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echo -e "Testing implicit Verilog generation";
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2020-07-27 18:18:59 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/implicit_verilog --debug --show_thread_logs
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2020-04-12 21:00:20 -05:00
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2020-04-12 21:06:40 -05:00
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echo -e "Testing Verilog generation with flatten routing modules";
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2020-07-27 18:18:59 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/flatten_routing --debug --show_thread_logs
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2020-04-12 21:06:40 -05:00
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2020-04-12 21:10:51 -05:00
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echo -e "Testing Verilog generation with duplicated grid output pins";
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2020-07-27 18:18:59 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/duplicated_grid_pin --debug --show_thread_logs
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2020-04-12 21:10:51 -05:00
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2020-04-22 15:42:30 -05:00
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echo -e "Testing Verilog generation with spy output pads";
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2020-07-27 18:18:59 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/spypad --debug --show_thread_logs
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2020-04-22 15:42:30 -05:00
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2020-06-12 12:38:05 -05:00
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2020-07-22 21:22:59 -05:00
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echo -e "Testing Power-gating designs";
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2020-07-27 18:18:59 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug
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2020-07-22 21:22:59 -05:00
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2020-07-24 19:07:12 -05:00
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echo -e "Testing Depopulated crossbar in local routing";
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2020-07-27 18:18:59 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/depopulate_crossbar --debug --show_thread_logs
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2020-07-24 19:07:12 -05:00
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2020-09-16 18:35:49 -05:00
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echo -e "Testing Fully connected output crossbar in local routing";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs
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2020-08-19 21:04:01 -05:00
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echo -e "Testing through channels in tileable routing";
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2020-08-19 21:11:37 -05:00
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs
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2020-08-19 21:04:01 -05:00
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2020-04-28 19:16:52 -05:00
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# Verify MCNC big20 benchmark suite with ModelSim
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# Please make sure you have ModelSim installed in the environment
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# Otherwise, it will fail
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2020-07-27 18:18:59 -05:00
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#python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mcnc_big20 --debug --show_thread_logs --maxthreads 20
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2020-07-04 20:06:41 -05:00
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#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim
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2020-04-28 19:16:52 -05:00
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2019-08-31 23:36:18 -05:00
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end_section "OpenFPGA.TaskTun"
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