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OpenFPGA/.travis/fpga_verilog_reg_test.sh

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add missing files for Travis
2019-04-10 02:24:37 -05:00
#!/bin/bash
set -e
Added travis fold for Python Task [ci skip]
2019-08-31 23:36:18 -05:00
start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
remove simulation settings from openfpga arch XML update travis to split CI tests fix errors in travis configuration fixing travis errors in scripts keep fixing travis fix travis on build.sh bug fixing in travis CI bug fix in travis regression test run fixing bugs in the travis scripts bug fix in travis script: remove common.sh in regression test call keep bug fixing in travis
2020-06-11 13:05:12 -05:00
cd ${TRAVIS_BUILD_DIR}
add duplicate_grid_pin to travis integration
2019-12-30 15:06:20 -06:00
deploy openfpga shell in Travis CI
2020-04-12 13:57:13 -05:00
###############################################
# OpenFPGA Shell with VPR8
##############################################
refactored CI for split regression tests in terms of OpenFPGA tools
2020-07-27 18:05:46 -05:00
echo -e "FPGA-Verilog Feature Tests";
deploy the tests to CI
2020-05-04 13:36:06 -05:00
add more test cases about LUT design and deploy to CI
2020-05-01 16:05:59 -05:00
echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/single_mode --debug --show_thread_logs
deploy single mode in regression tests
2020-04-20 14:16:52 -05:00
add more test cases about LUT design and deploy to CI
2020-05-01 16:05:59 -05:00
echo -e "Testing Verilog generation for LUTs: simple fracturable LUT6 ";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut --debug --show_thread_logs
add more test cases about LUT design and deploy to CI
2020-05-01 16:05:59 -05:00
echo -e "Testing Verilog generation for LUTs: LUT6 with intermediate buffers";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/intermediate_buffer --debug --show_thread_logs
deploy openfpga shell in Travis CI
2020-04-12 13:57:13 -05:00
add untileable test case to Travis CI
2020-04-12 15:08:24 -05:00
echo -e "Testing Verilog generation with VPR's untileable routing architecture ";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/untileable --debug --show_thread_logs
add untileable test case to Travis CI
2020-04-12 15:08:24 -05:00
add test case of BRAM to Travis CI
2020-04-12 15:27:05 -05:00
echo -e "Testing Verilog generation with hard adder chain in CLBs ";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/hard_adder --debug --show_thread_logs
add test case of BRAM to Travis CI
2020-04-12 15:27:05 -05:00
echo -e "Testing Verilog generation with 16k block RAMs ";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/dpram16k --debug --show_thread_logs
add test case of BRAM to Travis CI
2020-04-12 15:27:05 -05:00
add test case of wide BRAM 16k to Travis CI
2020-04-12 15:37:08 -05:00
echo -e "Testing Verilog generation with 16k block RAMs spanning two columns ";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/wide_dpram16k --debug --show_thread_logs
add test case of wide BRAM 16k to Travis CI
2020-04-12 15:37:08 -05:00
add io test cases to Travis CI
2020-04-12 16:01:47 -05:00
echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA ";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/multi_io_capacity --debug --show_thread_logs
add io test cases to Travis CI
2020-04-12 16:01:47 -05:00
echo -e "Testing Verilog generation with I/Os only on left and right sides of an FPGA ";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/reduced_io --debug --show_thread_logs
add io test cases to Travis CI
2020-04-12 16:01:47 -05:00
add long adder chain to Travis CI
2020-04-12 16:43:19 -05:00
echo -e "Testing Verilog generation with adder chain across an FPGA";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/adder_chain --debug --show_thread_logs
add long adder chain to Travis CI
2020-04-12 16:43:19 -05:00
add register chain and scan chain to Travis CI
2020-04-12 16:28:22 -05:00
echo -e "Testing Verilog generation with shift register chain across an FPGA";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/register_chain --debug --show_thread_logs
add register chain and scan chain to Travis CI
2020-04-12 16:28:22 -05:00
echo -e "Testing Verilog generation with scan chain across an FPGA";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/scan_chain --debug --show_thread_logs
add register chain and scan chain to Travis CI
2020-04-12 16:28:22 -05:00
refactored CI for split regression tests in terms of OpenFPGA tools
2020-07-27 18:05:46 -05:00
echo -e "Testing Verilog generation with routing multiplexers implemented by tree structure";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/tree_structure --debug --show_thread_logs
add test cases on different routing multiplexer circuit designs to Travis CI
2020-04-12 16:39:45 -05:00
refactored CI for split regression tests in terms of OpenFPGA tools
2020-07-27 18:05:46 -05:00
echo -e "Testing Verilog generation with routing multiplexers implemented by standard cell MUX2";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/stdcell_mux2 --debug --show_thread_logs
add test cases on different routing multiplexer circuit designs to Travis CI
2020-04-12 16:39:45 -05:00
refactored CI for split regression tests in terms of OpenFPGA tools
2020-07-27 18:05:46 -05:00
echo -e "Testing Verilog generation with routing multiplexers implemented by local encoders";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/local_encoder --debug --show_thread_logs
deploy local encoder to CI
2020-05-01 15:56:07 -05:00
[Regression Test] Deploy the debuf mux test case to CI
2020-09-14 16:48:08 -05:00
echo -e "Testing Verilog generation with routing multiplexers without buffers";
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/debuf_mux --debug --show_thread_logs
[Regression Test] Deploy input buffer only multiplexer testcase to CI
2020-09-14 17:11:48 -05:00
echo -e "Testing Verilog generation with routing multiplexers with input buffers only";
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs
add behavioral verilog test case to Travis CI
2020-04-12 20:55:47 -05:00
echo -e "Testing Verilog generation with behavioral description";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs
add behavioral verilog test case to Travis CI
2020-04-12 20:55:47 -05:00
add implicit verilog test case to Travis CI
2020-04-12 21:00:20 -05:00
echo -e "Testing implicit Verilog generation";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/implicit_verilog --debug --show_thread_logs
add implicit verilog test case to Travis CI
2020-04-12 21:00:20 -05:00
add flatten routing test case to Travis CI
2020-04-12 21:06:40 -05:00
echo -e "Testing Verilog generation with flatten routing modules";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/flatten_routing --debug --show_thread_logs
add flatten routing test case to Travis CI
2020-04-12 21:06:40 -05:00
add duplicated_grid_pin test case to Travis CI
2020-04-12 21:10:51 -05:00
echo -e "Testing Verilog generation with duplicated grid output pins";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/duplicated_grid_pin --debug --show_thread_logs
add duplicated_grid_pin test case to Travis CI
2020-04-12 21:10:51 -05:00
add spypad to regression test
2020-04-22 15:42:30 -05:00
echo -e "Testing Verilog generation with spy output pads";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/spypad --debug --show_thread_logs
add spypad to regression test
2020-04-22 15:42:30 -05:00
deploy fabric key test cases to CI
2020-06-12 12:38:05 -05:00
echo -e "Testing Secured FPGA fabrics";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/generate_vanilla_key --debug --show_thread_logs
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/generate_random_key --debug --show_thread_logs
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/load_external_key --debug --show_thread_logs
deploy fabric key test cases to CI
2020-06-12 12:38:05 -05:00
deploy power gating test cases to CI
2020-07-22 21:22:59 -05:00
echo -e "Testing Power-gating designs";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug
deploy power gating test cases to CI
2020-07-22 21:22:59 -05:00
deploy depopulated crossbar test case in CI
2020-07-24 19:07:12 -05:00
echo -e "Testing Depopulated crossbar in local routing";
classify regression test to dedicated categories
2020-07-27 18:18:59 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/depopulate_crossbar --debug --show_thread_logs
deploy depopulated crossbar test case in CI
2020-07-24 19:07:12 -05:00
deploy through channel test case to CI
2020-08-19 21:04:01 -05:00
echo -e "Testing through channels in tileable routing";
[regression test] Add more tests for thru channels and deploy to CI
2020-08-19 21:11:37 -05:00
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs
deploy through channel test case to CI
2020-08-19 21:04:01 -05:00
update travis script with example run on MCNC big20
2020-04-28 19:16:52 -05:00
# Verify MCNC big20 benchmark suite with ModelSim
# Please make sure you have ModelSim installed in the environment
# Otherwise, it will fail
classify regression test to dedicated categories
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#python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mcnc_big20 --debug --show_thread_logs --maxthreads 20
Reorganize task directory
2020-07-04 20:06:41 -05:00
#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim
update travis script with example run on MCNC big20
2020-04-28 19:16:52 -05:00
Added travis fold for Python Task [ci skip]
2019-08-31 23:36:18 -05:00
end_section "OpenFPGA.TaskTun"