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OpenFPGA/openfpga/src/fpga_verilog/verilog_api.h

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start transplanting fpga_verilog
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#ifndef VERILOG_API_H
#define VERILOG_API_H
/********************************************************************
* Include header files that are required by function declaration
*******************************************************************/
#include <string>
#include <vector>
#include "mux_library.h"
add architecture decoder (for frame-based config memory) to Verilog writer
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#include "decoder_library.h"
start transplanting fpga_verilog
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#include "circuit_library.h"
[OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol
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#include "config_protocol.h"
add grid module Verilog writer
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#include "vpr_context.h"
#include "vpr_device_annotation.h"
start transplanting fpga_verilog
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#include "device_rr_gsb.h"
plug in netlist manager and now the include_netlist appears in one unique file
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#include "netlist_manager.h"
start transplanting fpga_verilog
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#include "module_manager.h"
ported verilog testbench generator online. Split from fabric generator. Testing to be done
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#include "bitstream_manager.h"
add fabric bitstream data structure and deploy it to Verilog testbench generation
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#include "fabric_bitstream.h"
ported verilog testbench generator online. Split from fabric generator. Testing to be done
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#include "simulation_setting.h"
[Tool] Deploy pin constraints to preconfig Verilog module generation
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#include "pin_constraints.h"
ported verilog testbench generator online. Split from fabric generator. Testing to be done
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#include "io_location_map.h"
[Tool] Use use standard data structure to store global port information
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#include "fabric_global_port_info.h"
bug fix for using renamed i/o names
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#include "vpr_netlist_annotation.h"
[FPGA-Verilog] Now FPGA-Verilog can output shift register bank netlists
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#include "memory_bank_shift_register_banks.h"
[FPGA-Verilog] Adding bus group support in Verilog testbenches
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#include "bus_group.h"
ported verilog testbench generator online. Split from fabric generator. Testing to be done
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#include "fabric_verilog_options.h"
#include "verilog_testbench_options.h"
start transplanting fpga_verilog
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/********************************************************************
* Function declaration
*******************************************************************/
/* begin namespace openfpga */
namespace openfpga {
adapt all the Verilog submodule writers and bring it onlien
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void fpga_fabric_verilog(ModuleManager& module_manager,
plug in netlist manager and now the include_netlist appears in one unique file
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NetlistManager& netlist_manager,
[Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface
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const MemoryBankShiftRegisterBanks& blwl_sr_banks,
bring fpga verilog create directory online
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const CircuitLibrary& circuit_lib,
const MuxLibrary& mux_lib,
add architecture decoder (for frame-based config memory) to Verilog writer
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const DecoderLibrary& decoder_lib,
add grid module Verilog writer
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const DeviceContext& device_ctx,
const VprDeviceAnnotation& device_annotation,
bring fpga verilog create directory online
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const DeviceRRGSB& device_rr_gsb,
add option data structure for FPGA Verilog
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const FabricVerilogOption& options);
start transplanting fpga_verilog
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[Tool] Add a new command write_full_testbench which outputs self-testable full testbench which loads external bitstream file; Currently only support configuration chain without fast configuration technique
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int fpga_verilog_full_testbench(const ModuleManager& module_manager,
const BitstreamManager& bitstream_manager,
const FabricBitstream& fabric_bitstream,
[FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank
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const MemoryBankShiftRegisterBanks& blwl_sr_banks,
[Tool] Add a new command write_full_testbench which outputs self-testable full testbench which loads external bitstream file; Currently only support configuration chain without fast configuration technique
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const AtomContext& atom_ctx,
const PlacementContext& place_ctx,
const PinConstraints& pin_constraints,
[FPGA-Verilog] Adding bus group support in Verilog testbenches
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const BusGroup& bus_group,
[Tool] Add a new command write_full_testbench which outputs self-testable full testbench which loads external bitstream file; Currently only support configuration chain without fast configuration technique
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const std::string& bitstream_file,
const IoLocationMap& io_location_map,
const FabricGlobalPortInfo &fabric_global_port_info,
const VprNetlistAnnotation& netlist_annotation,
const CircuitLibrary& circuit_lib,
const SimulationSetting& simulation_parameters,
const ConfigProtocol& config_protocol,
const VerilogTestbenchOption& options);
ported verilog testbench generator online. Split from fabric generator. Testing to be done
2020-02-27 13:33:09 -06:00
[Tool] Add a new command 'write_preconfigured_fabric_wrapper'
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int fpga_verilog_preconfigured_fabric_wrapper(const ModuleManager &module_manager,
const BitstreamManager &bitstream_manager,
const AtomContext &atom_ctx,
const PlacementContext &place_ctx,
const PinConstraints& pin_constraints,
[FPGA-Verilog] Adding bus group support in Verilog testbenches
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const BusGroup& bus_group,
[Tool] Add a new command 'write_preconfigured_fabric_wrapper'
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const IoLocationMap &io_location_map,
const FabricGlobalPortInfo &fabric_global_port_info,
const VprNetlistAnnotation &netlist_annotation,
const CircuitLibrary &circuit_lib,
const ConfigProtocol &config_protocol,
const VerilogTestbenchOption &options);
[Tool] Add a new command 'write_preconfigured_testbench'
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int fpga_verilog_preconfigured_testbench(const ModuleManager &module_manager,
const AtomContext &atom_ctx,
const PinConstraints& pin_constraints,
[FPGA-Verilog] Adding bus group support to all Verilog testbench generators
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const BusGroup& bus_group,
[Tool] Add a new command 'write_preconfigured_testbench'
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const FabricGlobalPortInfo &fabric_global_port_info,
const VprNetlistAnnotation &netlist_annotation,
const SimulationSetting &simulation_setting,
const VerilogTestbenchOption &options);
[Tool] Add a new command 'write_preconfigured_fabric_wrapper'
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[Tool] Add a new command 'write_simulation_task_info'
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int fpga_verilog_simulation_task_info(const ModuleManager &module_manager,
const BitstreamManager &bitstream_manager,
const AtomContext &atom_ctx,
const PlacementContext &place_ctx,
const IoLocationMap &io_location_map,
const SimulationSetting &simulation_setting,
const ConfigProtocol &config_protocol,
const VerilogTestbenchOption &options);
start transplanting fpga_verilog
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} /* end namespace openfpga */
#endif