2020-01-29 15:29:00 -06:00
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/********************************************************************
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* Header file for circuit_library_utils.cpp
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*******************************************************************/
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#ifndef CIRCUIT_LIBRARY_UTILS_H
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#define CIRCUIT_LIBRARY_UTILS_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include <vector>
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#include "circuit_library.h"
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2021-09-23 16:39:16 -05:00
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#include "config_protocol.h"
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2020-01-29 15:29:00 -06:00
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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std::vector<CircuitModelId> find_circuit_sram_models(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model);
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std::vector<CircuitPortId> find_circuit_regular_sram_ports(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model);
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std::vector<CircuitPortId> find_circuit_mode_select_sram_ports(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model);
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size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model,
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const e_config_protocol_type& sram_orgz_type);
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2020-05-28 14:09:01 -05:00
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size_t find_circuit_num_config_bits(const e_config_protocol_type& config_protocol_type,
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const CircuitLibrary& circuit_lib,
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2020-01-29 15:29:00 -06:00
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const CircuitModelId& circuit_model);
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std::vector<CircuitPortId> find_circuit_library_global_ports(const CircuitLibrary& circuit_lib);
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std::vector<std::string> find_circuit_library_unique_verilog_netlists(const CircuitLibrary& circuit_lib);
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2020-09-20 13:53:28 -05:00
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std::vector<std::string> find_circuit_library_unique_spice_netlists(const CircuitLibrary& circuit_lib);
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2021-09-23 16:39:16 -05:00
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bool check_configurable_memory_circuit_model(const ConfigProtocol& config_protocol,
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const CircuitLibrary& circuit_lib);
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2020-05-25 20:02:14 -05:00
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2020-07-22 19:47:12 -05:00
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CircuitPortId find_circuit_model_power_gate_en_port(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model);
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CircuitPortId find_circuit_model_power_gate_enb_port(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model);
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2021-02-09 21:23:05 -06:00
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std::vector<CircuitPortId> find_lut_circuit_model_input_port(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model,
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const bool& include_harden_port,
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const bool& include_global_port = true);
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std::vector<CircuitPortId> find_lut_circuit_model_output_port(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model,
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const bool& include_harden_port,
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const bool& include_global_port = true);
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2020-01-29 15:29:00 -06:00
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} /* end namespace openfpga */
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#endif
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