tangxifan
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8c281a22b0
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[Engine] Add check codes to validate circuit models for BL/WL protocols
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2021-09-23 14:39:16 -07:00 |
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tangxifan
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6a0f4f354f
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[Tool] Support superLUT circuit model in core engine
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2021-02-09 20:23:05 -07:00 |
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tangxifan
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222bc86cbf
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[FPGA-SPICE] Add auxiliary SPICE netlist writer
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2020-09-20 12:53:28 -06:00 |
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tangxifan
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f573fa3ee0
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move check codes on power gate ports to libarchopenfpga
Try to report errors to users as early as possible
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2020-07-22 18:47:12 -06:00 |
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tangxifan
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bf9f62f0f7
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keep bug fixing for frame-based configuration protocol.
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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3a26bb5eef
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add advanced check in configurable memories
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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f11832b8cf
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start integrating module graph builder
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2020-02-12 17:53:23 -07:00 |
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tangxifan
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d2c47693f6
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add check codes for mode bits annotation to pb_types and clean up utils source files
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2020-01-29 14:29:00 -07:00 |