* New: In CRL Core, remove obsoleted XML files, no longer needed by
Chams. Add stub for technologies CMOS065 (ST) and C35B4, aka
AMS 035.
* Bug: In Knik, update the path where to find the FLUTE lookup tables.
(from 2.4 to 3.1).
* New: In Hurricane, In CellWidget, add methods to emit CellPreModificated
and CellPostModificated Qt signals (from non-Qt aware objects).
* New: In Unicorn, In ImportCell, parsers are now dynamically hooked
in the importer, allowing third party application (i.e. Chams) to
add their own. See the ImportCell::addImporter() method.
* Bug: In Unicorn, in FindUNICORN.cmake, seems to be unable to detect
the UnicornGui.h. Not a blocking problem because the include dir
is shared with other tools correctly detected. But still...
* New: In VLSISAPD, in Configuration, add a new priority level UserFile
to distinguish between the system configuration files and the user's
configuration files (which take precedence).
* New: In Hurricane, in Script (Python), improve the API to be able
to support Chams (and remove the duplicate capability from it).
Add separate functions to perform the initialize/run(s)/finalize
cycle step by step.
* Change: In CRL Core, rename real technology <hcmos9> to <hcmos9gp>,
it's offcial name from CMP/ST. This is the 130nm.
Move the reading of the symbolic & real technologies names from
coriolisInit.py to helpers.__init__.py, to be shared with
chamsInit.py.
To avoid a clash of names inside of helpers, the two variables
of techno.py are renamed "symbolicTechnology" and "realTechnology".
Move python init system from crlcore/src/crlcore to crlcore/python.
* New: In CRL Core, In Utilities, add site-packages/pharos to the
PYTHONPATH.
* Change: In Kite, move python init system from kite/src/init to
kite/python.
* Bug: In CRL Core, in Ispd05Bookshelf, as the pitch is already expressed
in DbU, do not apply DbU::toLambda() in any expression where it is used.
* Change: In Etesian, In AddFeeds, do not try insert feeds if there is no
cell feed avalaible.
* Change: In Bootstrap & ccb, the coloquinte project is renamed into
"importeds", it will be the home of all the externally
devellopped softwares that are needed to build Coriolis.
Add explicit support for Fedora ("Linux.fc") and uses
site-packages, as everybody else.
* New: In CRL Core, in etc/, adds the configuration files for Etesian.
* New: In Etesian, activate the Configuration object. Now uses it's
own configuration variables instead of borrowing those of
Nimbus & Mauka.
* Change: In Documentation, updated User's Guide to present Etesian
as the placer, instead of Mauka.
* Change: In Cumulus, slight change in ClokTreePlugin and ChipPlugin
to match the new Etesian/Python interface.
* New: In Bootstrap, in ccb.py, check if cmake is installed and issue
a warning, if not.
* New: In Hurricane, added Cell::getDeepNet() to search for a deepnet
given a path and a leaf net. This method is slow and must not be
used too often. Introduced for Kite::BuildPowerRails().
* Change: In CRL Core, in cmos/alliance.conf, modify the clock name
pattern to match the sub-clock signals in the datapath operators.
* Bug: In Etesian, do not blindly reset the top cell abutment-box.
Do it only if it's empty, otherwise keep it.
* Bug: In Kite, in buildPowerRails(), in getRootNet() the management
of clock nets was incomplete. The case of unrouted clock nets
that where not connected to the top core clock net, like the
one in the datapath registers was faulty. They were partly
recognized as unrouteds and partly as blockage generating a
routing deadlock: routage impossible due to blockage generated
from itself...
* New: In Stratus1, add a buildModel() utility function to automate
the model generation and allow a call by the model name (string).
* Change: In Unicorn, in cgt.py, display the Alliance environement.
* New: In Hurricane, in DebugSession, add a new method to activate the
trace inconditionally with a certain level.
* New: In Hurricane, in HyperNet, allow copy construction as there is
no reason to disallow it and we need it now.
* New: In Hurricane, in Cell::flattenNets(), add a new option to prevent
the flattening of the clock net(s). For more safety perform the
DeepNet creation *outside* the Collection loop.
* Bug: In Hurricane, in Cell_HyperNetRootNetOccurrences, skip the
DeepNets because they are the result of another flattening operation.
* New: In Isobar, in PyBasicLayer, export C++ method getBlockageLayer().
* New: In Isobar, in PyRoutingGauge, export C++ method getLayerPitch(),
needed by Cumulus plugins.
* New: In Etesian, EtesianEngine::findYSpin() to look for the Y orientation
if some cells are already placed. Typically the buffers of a clock
tree.
Pass the correct orienation to row_compatible_orientation().
Do not try to add feeds in the ISPD05 benchmarks. For now the
benchmarks are detected through their names (unreliable).
* Change: In Knik, in KnikEngine::initGlobalRouting(), allow the clock
to be routed as an ordinary signal when the clock tree is not
used.
* New: In Kite, in BuildPowerRails, management & detection for the
pre-routed clock.
In KiteEngine constructor, early initialization of the blockage
net to avoid later troubles in BuildPowerRails.
* New: In Cumulus, in ChipPlugin, add support for Etesian plus new
configuration parameter 'clockTree.placerEngine' to select between
Mauka and Etesian.
* New: In Cumulus, in BlockCorona, add blockages in the vertical sides
in the vertical layer to prevent the router to use the vertical
tracks in under the prower lines (for example, blockage in M3
with power line M5).
In Cumulus, in ChipConf add attribute to access the blockage net.
* New: In Cumulus, when the clock tree is disabled, do not generate
the last rail around the block (the clock rail).
* Bug: In Cumulus, in ChipConf use the clock pad to guess the clock
signals and *not* the power pad.
Add more meaningful error messages if a pad global signal is
not found (implicit connexion by name).
* Bug: In Cumulus, in ClockTree, compute correctly the cells Y spin,
that is *from the bottom of the cell AB* (not from 'zero').
* Bug: In Bootstrap, in coriolisEnv.py, check if devtoolset-2 is already
active before launching it as a sub-shell.
* Bug: In Isobar, In PyHurricane.h, DBoDestroyAttribute() set the proxy
pointer toward the C++ object to NULL. So when the Python object is
deleted no double-deletion occurs on the C++ object.
Add some more trace information in Python link/dealloc.
* Change: In CRL Core, in cyclop, make CMakeLists.txt automatically
choose the right rule for linking the binary wether we use Qt 4 or
Qt 5. Very irksome problem.
* New: In EtesianEngine::addFeed(), do not take into account instances
that are not placed entirely inside the top cell abutment box (was
causing a core dump).
* Bug: In Katabatic, in GCellQueue, correct a mismatch between a GCell
set and the iterators used upon it.
* Bug: In Mauka, in Row & Surface correct a mismatch between a container
and it's iterator.
* New: In Etesian, updated to work with the latest Coloquinte, patch
contributed by G. Gouvine.
Added EtesianEngine::setDefaultAb() to compute an abutment box if
the Cell is completly unplaced.
* New: In cumulus, in ClockTree, now the placer can be configured to be
either Mauka (slow simulated annealing) or Etesian (fast analytic).
New setting 'clockTree.placerEngine' in plugin settings.
* New: In Bootstrap, in Builder & coriolisEnv.py support for RHEL7/SL7.
The sub-directory name is 'el7_64'.
In qt_setup() add QtSvg to list of Qt5 & Qt4 used libraries.
* New: In Hurricane, In Cell add a placeholder for flags. First use to
store whether the Nets have been transhierarchically flatteneds.
* New: In Hurricane, In NetRoutingState add an Unconnected flag for
more accurate diagnosis.
* New: Hurricane, in CellViewer add an entry menu for stress tests.
The script must be named "stressScript.py" in the cwd.
* Change: In CRL Core, in display.conf add a scaling parameter for the
display threhold of the layer. This way we can adapt to different
standard cells height.
* Change: In CRL Core, in ISPD05 bookshelf loader, use the pitch of the
cell gauge instead of a hard-wired 5.0.
* Change: In Cumulus, in ClockTreePlugin, add support for Etesian placer
and a new configuration parameter to choose between Mauka/Etesian.
* New: In Etesian, support for the latest Coloquinte.
Add feed insertion stage.
* Bug: In Kite, In BuildPowerRails, check that _ck is not NULL before
tring to access it's name...
* Change: In Kite, check if the Cell has it's Nets flattened before
doing it (or not).
* Change: In CRL Core, in VstParserGrammar.yy display in which mode a file
is read. Behavioral, structural or model. Model is the step of reading
the instance's models before truly reading the file.
In addition, a small optimization, when in behavioral mode, parse
the file only once.
* Bug: In CRL Core, in VstParserGrammar.yy & VstParserScanner.ll, accurate
error message positions (file & line numbers).
When generating error message, we cannot pass char* on variables that
will be deallocated by the throw. So generate a string that will be
copied along with the exception. That problems explain numerous
core-dump when encountering syntaxes errors in the file.
* New: In Bootstrap, added support for RHEL7 in ccb.py & coriolisEnv.py.
In coriolisEnv.py, under RHEL6, directly launch a shell under
devtoolset-2 (do not put it in .bashrc).
* Change: All tools, compliance with Clang 3.2.
- Call using namespace std *after* at least one include of std has
been used.
- In Utilities.h define both const and non-cont overload for operator<<
of mstream (this was the true cause of the Banner display problem).
- No longer use defaults arguments in templates, instead create two
separated overloads.
- Put template static attributes allocation outside of namespaces
(this one I'm not sure how to justify).
- Protect by NDEBUG variables that are only needed in assert().
- In PyInterval getUnion() & getIntersection() we where silently
overwriting the "self" object (interval).
- In Mauka, *do no* overload _postCreate() and add an argument, breaks
the virtual function mechanism. Rename it into _maukaPostCreate().
Idem for SubRow().
- In Katabatic::GCell(), invalidate() overload a Go funtion but is
used for different purpose at this level. Rename it invalidateCt()
(invalidate *ConTents*).
- Miscellaneous small cleanup.
* Change: In CRL Core, in coriolisInit.py now read the configuration
files from a ".coriolis2/" directory. This is to avoid too many
dot files in the user's directory. Files have also been renamed:
.coriolis2.conf ==> .coriolis2/settings.conf
.coriolis2_techno.conf ==> .coriolis2/techno.conf
* Change: In Kite, in kiteInit.py follow the same policy as CRL Core
for configuration file.
.coriolis2.kite.py ==> .coriolis2/kite.py
* Change: In Hurricane, the NetRoutingProperty is moved into Hurricane
from Katabatic. Needed for Knik to be able to access thoses
informations.
* Change: In Hurricane, in RoutingPad::setOnBestComponent(), now in
case of identical area, select the component of lowest id.
This should not be needed if the component ordering was fully
deterministic as it should be (will investigate later).
This is to ensure that the choosen component is always the
same, especially between save/load of a global routing.
* Bug: In Katabatic, in AutoContactHTee::updateTopology(), invalidate
the segments only if the topology is valid (no NULL in the
cached segments).
* Bug: In Katabatic, in GCellTopology::construct(), throw an error
if the topology is bad instead of trying to continue (and core
dump later... ).
* Bug: In Kite, in BuildPowerRails, distinguish the name of the master
net in the pad (for vddi, vssi, vdde, vsse, ck, cki & cko) and the
name of the net in the *chip* netlist. Must use the later to make
comparison as they may differs.
* Change: In Knik, in save/load solution, exclude nets that are not
globally routed by Knik. That is which NetRoutingProperty is not
*Automatic*.
* Bug: In Cumulus, in chip.BlockPower take account of the layer
width extention to sligthy shrink the connector thus avoiding a
notch with standart cell in some cases.
* Change: In Cumulus, in chip.ClockTree disable the use of fixed Steiner
trees for the leaf clocks, as it seems overconstrained for the
router. First move was to lower them in M2/M3 (instead of M3/M4)
but that was not sufficent.
* New: In Cumulus, RSavePlugin for recursively saving a physical
hierarchy.
* New: In documentation, first embryo for RDS file. Should have been
in Alliance git, but I prefer to keep newest doc in Coriolis.
* New: In CRL Core, in helpers & alliance.conf, set and read a "PAD"
variable to define the pad model name extension ("px" for "sxlib
and "pxr" for vsxlib, this is provisional).
* New: In CRL Core, in plugin.conf, add parameters to define the name
of used for power & clock supply. We may remove the extention in
the future (to be more coherent with the previous modification).
* New: In Cumulus, in chip.Configuration.GaugeConf._rpAccess(), no
longer place the accessing contact *at the center* of the
RoutingPad. It works under sxlib because buffers & registers all
have same size terminals. But this is not true under vsxlib,
leading to misaligned contacts & wires. Now systematically place
on the slice midlle track (maybe with one pitch above or below).
This is still very weak as we do not check if the terminal
reach were the contact is being put. Has to be strenthened in
the future.
* New: In Cumulus, in chip.Configuration.ChipConf, read the new
clock & power pad parameters.
* Change: In Isobar (and all other Python wrappers), uses PyLong instead
of PyInt for DbU conversions. In PyHurricane argument converter,
automatically check for both PyLong and then PyInt.
* Change: In Cumulus, in chip.PadsCorona, more accurate error message
in case of discrepency in global net connections (i.e. no net
of the same name in instance model and instance model owner.
* Change: In Kite, in BuildPowerRails, when looking up at the pads
model name to find "pck_" or "pvddeck_", do not compare the
extension part. But we still use hard-coded stem pad names,
maybe we shouldn't.
* Bug: In Katabatic, in GCellConfiguration::_do_xG_xM1_xM3(), there
was a loop in the search of the best N/E initial RoutingPad.
* Bug: In Kite, in KiteEngine::protectRoutingPads(), *do not* protect
RoutingPads of fixed nets, they are already through the
BuildPowerRails stage (and it's causing scary overlap warning
messages).
* Bug: In Cumulus, in ClockTree.HTreeNode.addLeaf(), do not create
deep-plug when the core is flat (not sub-modules). All the new
nets are at core level.
* Bug: In Cumulus, in ChipPlugin.PlaceCore.doFloorplan(), ensure
that the core is aligned on the GCell grid (i.e. the slice
grid of the overall chip).
* Bug: In Kite, in GCellTopology::_do_xG_xM1_xM3(), infinite loop
while looking for the bigger N-E RoutingPad. Forgot to decrement
the index...
* New: In ClockTree plugin, select the name of the buffer cell through
configuration (parameter: "clockTree.buffer"), and guess the I/O
name of this buffer automatically.
Put configuration parameters in plugin.conf and not mauka.conf.
Bug: strangely triggers a coredump in components collection
when used with <vsxlib>. Some debug printing still active until
that is solved.
* New: In Chip plugin, make the size and numbers of the block rails
configuration parameters (in plugin.conf).
* Change: In Hurricane, in Plug::setNet(), more informative error messages.
* Change: In Hurricane, In Segment, more informative error messages.
* Change: In Hurricane, In DeepNet, accessor for the Net occurrence.
* Bug: In Katabatic, in AutoSegment::create(), error message uses correct
variables (vertical was using horizontal)...
* Change: In Kite, in BuildPowerRails, already existing wiring in instances
is copied up as blockage. Uses blockage layer instead of true layer
(it was a bug).
* Change: In Kite, in BuildPreRouted, consider as manual global routing
nets with only default wiring (default size wire & contacts).
Non-default routing is flagged as fixed (with the NetRoutingState
property).
* New: In Cumulus, first versions of the ClockTree and Chip plugins.
Clock Tree plugin:
- It is strongly advised to use have 4 metal routing layers for the
tree to work. Otherwise, problems can arise with the detailed
routing (fully obstructed terminals).
- H-Tree can only be build (for now) for design with a form factor
between 0.5 an 2.
- The tree is created at the block top-level and only the leafs are
trans-hierarchically created on the instances/models. The new
cell with a clock tree, along with all it's sub-models is created
with a "_clocked" suffix.
- Leaf cells are connected through a simple Minimum Steiner Tree.
- Shorts are avoided by a systematic shift of the wires according
to their kind. No wire must pre-exist. When used as a sub-module
of "chip" the wires cannot be moved. When created on a block,
the wires can be loaded in the detailed router as manual global
router.
Chip Plugin:
- Perform the pad placement and corona creation. Replacement at
last of the clunky code from Wu Yifei.
- Relies on a Python configuration file '<design>_chip.py' with
a "chip" dictionnary.
* Bug: In CRL Core, in agdsDriver, the flags of the Query where sets to
process only the top-level Cell. Now process the whole hierarchy (the
Cell is completly flattened by this operation). Secondary bug: the
transformation was not applied to the bounding boxes, resulting of
all the cells stacked in (0,0) ...
* New: In CRL Core, added configuration for SCMOS_DEEP symbolic technology
up to 180nm "scmos_deep_018". It is postfixed "_018" because it is not
yet compliant with 130nm (asymetrical VIA metal extensions).
Added the associated real technology SCN6M_DEEP (TSMC 180nm).
* Change: In CRL Core, in Alliance.py, no longer requires the
configuration file to uses symbols from CRL.Environment or
CRL.RoutingLayerGauge. This way the <alliance.conf> file can be
parsed by a different parser.
In <alliance.conf>, for the various technologies, make uses
of the new C++ independent constants.
* New: In CRL Core, in helpers/__init__.py, provide a "Dots" class
(rewrite the C++ one in pure Python).
* New: In Unicorn, in ExportCellDialog and UnicornGui add an entry to
call the ASCII/GDSII export driver.
* New: In CRL Core, in AgdsDriver, checks for off-grid coordinates (that
is non-integer one) and round them with a warning. This is most
likely that the layout is flawed but it will at leat generate a
readable ASCII/GDSII file.
* New: In Cumulus, new Alliance.py module (*not* a plugin) providing
an encapsulation for Alliance command line tools. The other main
feature is that it provides a "Makefile like" behavior. Based on
the command dependencies a DAG is contructed, then a static
ordering of the commands. Commands are then executed to rebuild
outdated target.
The Alliance environment supplied to the commands is read from
the Coriolis configuration file <alliance.conf>.
For this first evaluation version, only <boom>, <boog> and
<loon> support are provided.
It still not clear how to encapsulate the Coriolis tools in
the same way.
* Change: In CRL Core, in helpers/__init__.py, change the way the static
initialization (module) is done. All the commands are put inside
a "staticInitialization()" function, which is then explicitly
called by others. This is a better solution agains *no* or *twice*
initialization. Modificate <coriolisInit.py> accordingly (as
<Alliance.py> from Cumulus.
* Change: In bootstrap, in ccb & builder, build by default with Qt4 and
provide a --qt5 command line switch to enable Qt5.
FindBootstrap.cmake now provides a qtX_wrap_cpp() macros to be
independant of the version of Qt being used.
Add all thoses options to the graphical interface to the builder.
* Change: In all the tools using Qt, switch to the qtX_*() macros from
FindBootstrap.cmake.
* Change: In Hurricane, in CellViewer, revert to the Qt4 way of connecting
signal/slots for backward compatibility.
Finally get rid of the demonic code from Wu Yifei...
* New: In Isobar, added encapsulation of Interval (don't know how have
forgotten it for so long).
* Change: In Isobar, In PyLayer, new PyLink_LayerDerived() function to
create/link the C++ object to the correct derived class and not the
base one (PyLayer) which then prevent to use the specialized methods.
Must replace PyLink_Layer() througout all the code.
* Change: In Isobar, in PyPoint the "setX()" & "setY()" methods where
still capitalized.
* Change: In Isobar, in PyQuery, complete the exportation of the C++
interface. remove the code belonging to a more "boost" way of
building the Python interface (will do that in a far future).
* New: In CRL Core, In PyAllianceFramework, export isPad() method.
* Change: In Unicorn, in unicornInit.py, protect the loading of each
single plugin by a "try" / "except" clause to the failing of one
plugins do not stop the loading of the next one.
Pass the same dictionnary argument to unicornHook() as for
ScripMain(), this is more uniform this way.
* New: In Cumulus, complete replacement of the chip placement scripts
from Wu Yifei (at last!). The clock-tree integration is still to
be done.
________________________________________________________________________
* New: In all to CMakeLists.txt, disable the warning about deprecated
WIN32 under cygwin.
* New: In boostrap, in ccb.py, coriolisEnv.py and builder/Configuration.py
add recognition in uname for the values returned under Windows/Cygwin.
* New: In Documenation, in UsersGuide.rst add some informations about
Cygwin and a section for the devel branch.
* New: In Kite, in protectCagedTerminal(), check that the perpandicular
top METAL3 track is free before inserting the fixed protection.
They are added *after* the Pre-Routed stage and therefore we have
to check they do not cross.
* Change: In Kite, in NegociateWindow, print statistics before fixing
segment in the pre-routed stage to get correct results.
* Change, In CRL Core, in Measures when an addMeasure is performed
twice, let the new data erase the previous one (instead of keeping
the previous one).
* New: In Katabatic, add the ability to decorate some (i.e. few) nets
with a state that indicate to Katabatic & Kite what to do with it.
The possible states are:
1. Fixed : all the wire are in fixed positions. The router cannot
move them and account them as obstacles.
2. ManualGlobalRoute : a user-defined topology is supplied. The
wires still have to be detailed route in "Detailed Pre-Route"
but will be skipped for the global routing and fixed for the
general Detailed route.
3. AutomaticGlobalRoute : ordinary nets, to be global routed then
detail routed.
4. Excluded : do not try to global or detail route thoses nets.
5. MixedPreRoute : mask combining Fixed and ManualGlobalRoute.
Not all nets have this property, only those that needs a special
processing.
To ease the access to the state, it is nested inside a
PrivateProperty in the net (NetRoutingProperty), with an extension
access class (NetRoutingExtension).
* New: In Kite, take account of NetRoutingState. Pointers to the
net's states are strored inside an internal map for faster access.
The property is *not* deleted when Kite is destroyed. The property
will remains until the Net itself is destroyed.
As a consequence, the lists that where passed to high level
function are removed as the information can now be accessed directly
through the net NetRoutingProperty.
* New: In Unicorn, in CgtMain, comply with the update interface.
* New: In documentation, update the User's Guide to explain the Pre-routed
step of Kite.
* Change: In Isobar, the Python interface was not exactly mirroring the
C++ one, now it is the case. The Python code should look likes almost
exactly like the C++ one, the only differences remaining being due
to the languages respective syntaxes. Note that in the case of
constructor functions, it leads to a slightly longer notation in
Python that it could have been (mimic the ".create()" static
member). Main modifications:
1. Mirror the static constructor syntax with create():
Cell( ... ) ==> Cell.create( ... )
2. Correct hierarchy for constants in Instance, Net, Pin
& Transformation. For example:
Hurricane.PlacementStatusFIXED
==> Hurricane.Instance.PlacementStatus.FIXED
Hurricane.OrientationID
==> Hurricane.Transformation.Orientation.ID
Hurricane.TypeLOGICAL ==> Hurricane.Net.Type.LOGICAL
Hurricane.DirectionIN ==> Hurricane.Net.Direction.IN
* Change: In CRL Core, correction to match the improved Python API
in the configutation helpers.
* Change: In Cumulus, correction to match the improved Python API.
* Change: In Stratus, correction to match the improved Python API.
* Change: In Documenation, update for the new Python interface
(both user's guide & examples).
* Note: We must port those changes into Chams for it to continue
to run.
* Change: In Documenation, update the Python script support part.
* New: In Hurricane, in CellViewer, create a simpler API to graft menu
and actions into the menubar. Mainly addToMenu() which take care of
the QAction creation but also locate the relevant QMenu, base on
the Qt object name. Regroup all the widget & action creation inside
the body of the constructor, this way almost all actions can be
removed from the attributes of the CellViewer.
addToMenu() is supplied in three flavors:
1. For C++ callbacks in GraphicToolEngines (with a binded
member function method).
2. For running Python scripts to be used by the plugin system.
3. To insert separator in menus (to give a more homogeneous
look).
Remove the last remnants of Stratus scripts (unificated with basic
Python scripts).
* New: In Hurricane, in PyCellViewer, export the interface to graft
Python scripts into the CellViewer menu tree.
* Change: In Etesian, in GraphicEtesianEngine, use the new API to
graft menus & callbacks into the CellViewer.
* Change: In Mauka, in GraphicMaukaEngine, use the new API to
graft menus & callbacks into the CellViewer.
* Change: In Kite, in GraphicKiteEngine, use the new API to
graft menus & callbacks into the CellViewer.
* New: In Cumulus, install Python scripts as plugins for Unicorn under
<PYTHON_SITE_PACKAGES>/cumulus/plugins/.
* New: In Unicorn, in UnicornGui, make uses of the new API for creating
menus in the CellViewer. Creates the stem menu for the P&R tools.
Add a Python initialization mechanism to read the plugins
installeds into <PYTHON_SITE_PACKAGES>/cumulus/plugins/.
* Change: In Kite, Katabatic & Knik, express the number of tracks truly
available to the global router by the number of tracks reserved to
the local routage inside a GCell. Replace the ratio parameter
"hEdgeCapacity" by an integer parameter "hTracksReservedLocal"
(duplicate for verticals).
It is more explicit to give directly the number of tracks that
are to be used locally, and potentially saves us from rouding
problems when calculating the number of availables tracks.
Note: we cannot do that for the layer saturateRatio as it
uses the density ratio that take account local wires, leading
to fractional results.
* Change: In Katabatic, in <GCellGrid>, rename checkEdgeSaturation()
into checkEdgeOverflow(), more explicit.
* Change: In Knik, in <Graph>, display the computed capacities of the
lower left node edges (should be the same througout all the grid).
* Change: In Unicorn, in <cgt.py>, uses the new parameters names for
edge density.
* New: In CRL Core, in PyCellGauge, add the missing methods.
* Bug: In Isobar, PyOccurrence_create(), the HTRY/HCATCH block was not
enclosing the constructor of Occurrence, which can throw exceptions.
When an exception was thown the Python interpreter just terminate
with the cryptic message:
"Fatal Python error: Py_EndInterpreter: thread still has a frame"
Reminder to myself: when such a message occurs, it means that the
interpreter did encounter a problem, but it's related to the isobar
interface.
Placement management:
* Change: In <metis>, always disable the hMetis support regardless of
it being detected or not as the placer is still unable manage the
final bin contents.
Routing gauge management:
* Bug: In CRL Core, <vsclib/alliance.conf>, set the correct pitches and
size for the routing layers and the cell gauge.
* Change: In Katabatic & Kite, extract the correct extension cap for each
routing layer from the layers characteristics (cache then in
Katabatic::Configuration).
* Change: In Katabatic, <AutoSegment>, create segment with the wire width
defined in the gauge. For AutoSegment created on already existing
Segment from the global routing, adjust the width.
* Change: In Katabatic, <AutoSegment>, more accurate information about how
a segment is connected to terminal via source and/or target.
The flag SegStrongTerminal is splitted into SegSourceTerminal and
SegSourceTarget (but still used as a mask). So now we can know by
which end an AutoSegment is connected to a terminal.
* Change: In Katabatic, ::doRp_Access(), create constraint freeing segments
not only when HSmall but also when VSmall (more critical for <vsclib>).
Otherwise we may see AutoSegments with incompatible source/target
constraints.
* Change: In Kite, BuildPowerRails, do not create blockage on PinOnly
layers *but* still create power rails planes. This is a temporary
workaround for <vsclib> where the METAL1 blockages overlaps the
terminals (it was fine for Nero, but they shouldn't for Kite).
* Change: In Kite, <RoutingEvent>, if a TrackSegment is overconstrained,
directly bybass it's slackening state to DataNegociate::Slacken.
Also rename the flag "_canHandleConstraints" to "_overConstrained",
seems clearer to me.
Miscellaneous:
* Change: In CRL Core, <Utilities>, add a "pass-though" capability on the
mstream to temporarily make them print everything.
Jean-Paul Chaput
Gabriel Gouvine