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  • 8d44f0d125 update build for newer binutils bfd syntax Ubuntu-20-04-qt5 Jeff Carr 2021-06-17 20:28:15 -0500
  • 72b5de88c4 Fix bugs in AutoSegment::isMiddleStack() and canReduce(). devel Jean-Paul Chaput 2021-06-17 23:49:54 +0200
  • ddc7aef13b At last make use of cdebug_log() in Track::repair(). Jean-Paul Chaput 2021-06-17 23:36:35 +0200
  • f873e616cb Use of tset() manipulator instead of setw() when printing in cdebug_log. Jean-Paul Chaput 2021-06-17 23:36:22 +0200
  • d43fa49778 Add basic support for logo insertion in cumulus/plugins.chip. Jean-Paul Chaput 2021-06-16 16:26:33 +0200
  • 15e7abf667 Use the DATATYPE for LAYER record in GdsStream. Jean-Paul Chaput 2021-06-16 16:24:01 +0200
  • 6c68055199 In core2chip, use the "padres" input of the analog pad. Jean-Paul Chaput 2021-06-15 01:18:41 +0200
  • c83fff72ac Suppress cell fitting during P&R. Jean-Paul Chaput 2021-06-15 01:17:01 +0200
  • ededad456f Merge branch 'classhier' into 'devel' Staf Verhaegen 2021-06-14 03:08:18 +0000
  • 2e015ea780 Prune ordinary wires in Katana::PowerRails. Jean-Paul Chaput 2021-06-13 12:03:57 +0200
  • 63d2f69459 Increate the reluctance to go up in Manipulator::moveUp(). Jean-Paul Chaput 2021-06-13 12:03:35 +0200
  • 1569e2807e In CRL::GdsParser, GDS layers indexes up to 1024, just in case. Jean-Paul Chaput 2021-06-12 17:52:29 +0200
  • f3ccf31e48 Fix incomplete GDS layer table in GdsParser. Jean-Paul Chaput 2021-06-12 16:29:08 +0200
  • 3bd1d56582 Fix last DRC incorrect case in TrackSegment::isMiddleStack(). Jean-Paul Chaput 2021-06-12 16:21:10 +0200
  • f9e4daace9 Comment out debug information in Track::repair(). Jean-Paul Chaput 2021-06-12 16:17:03 +0200
  • ffd6f571b5 No longer connect the root of HTrees with straigh lines, use the router. Jean-Paul Chaput 2021-06-12 11:49:07 +0200
  • 1733b5142a Fix bad index in Track::repair(). Jean-Paul Chaput 2021-06-12 11:42:53 +0200
  • ebe8ea64c6 Freeze version of RapidJSON to build under SL7. Jean-Paul Chaput 2021-06-11 11:47:35 +0200
  • 4e7dbee831 Fix HTree to corona's edge wiring in horizontal direction. Jean-Paul Chaput 2021-06-11 11:47:02 +0200
  • 68812fa0ca Fix same net gap between the two last elements of a Track. Jean-Paul Chaput 2021-06-11 11:46:37 +0200
  • 7c8d47a2d1 More generic criterion for finding under minimum area segments. Jean-Paul Chaput 2021-06-11 11:46:13 +0200
  • 9c153699be Merge branch 'devel' of gitlab.lip6.fr:vlsi-eda/coriolis into devel Jean-Paul Chaput 2021-06-10 15:29:31 +0200
  • 79858840fc In NetBuilderHV::_do_xG_1M1(), less rigid topology for straight vertical. Jean-Paul Chaput 2021-06-10 15:29:00 +0200
  • 19b9f9e2e7 put in a temporary absolutely terrible hack for now to skip adding analog pins Luke Kenneth Casson Leighton 2021-06-10 11:50:55 +0000
  • ed3bdbe455 un-messed-up IoSpecs.loadFromPinmux, add new function for making a pad Analog Luke Kenneth Casson Leighton 2021-06-10 11:46:30 +0000
  • ac3e78c55c allow ioSpecs loadFromPinmux to undersand IoPin.ANALOG format Luke Kenneth Casson Leighton 2021-06-10 11:13:27 +0000
  • 7961aab0e1 Adjust blockage area over SRAM. Jean-Paul Chaput 2021-06-09 15:11:43 +0200
  • 92a3e32aaf Add jumpers (antenna protection) on I/O pads and SRAM macro-block. Jean-Paul Chaput 2021-06-08 12:20:05 +0200
  • dd49a185af Compensate diodes between RP clusters & wire clusters. Jean-Paul Chaput 2021-06-08 12:19:40 +0200
  • 5f60767486 In AutoSegment::expandToMinLength(), ensure that we stay on foundry grid Jean-Paul Chaput 2021-06-08 12:19:08 +0200
  • 352ca94483 Change the way QuadTree.getLeafUnder() locate the leaf. Jean-Paul Chaput 2021-06-06 10:55:24 +0200
  • a2daf26fca Fix Block.getFlattenedNet() for "one instance path" cases. Jean-Paul Chaput 2021-06-06 10:50:13 +0200
  • fc445a2285 More comprehensive error message in VST parser (connector discrepencies). Jean-Paul Chaput 2021-06-06 10:46:39 +0200
  • 9b8ea64545 Add VHDL "ref" keyword to CRL::NamingScheme. Cleanup BlifParser debug. Jean-Paul Chaput 2021-06-04 11:28:12 +0200
  • 1d7a415e9f Fix memory corruption after placement occurring on LibreSOC/ls180. Jean-Paul Chaput 2021-06-03 01:20:24 +0200
  • d2a621629a Build blockages for all fixed nets in Katana. Jean-Paul Chaput 2021-06-02 14:53:45 +0200
  • d2e1ab3796 Add rgetInstanceMatching to utilities, as reminder and for later use. Jean-Paul Chaput 2021-06-02 14:16:45 +0200
  • 1afc48fb4c Forgot to update pointers to merged nets in BlifParser. Jean-Paul Chaput 2021-06-02 14:14:32 +0200
  • db26e14358 Add -fsanitize=address to the DEBUG flags. Jean-Paul Chaput 2021-06-02 14:14:11 +0200
  • fed586385c Do not connect HTree to I/O pad if the net is internal. Jean-Paul Chaput 2021-06-02 14:13:53 +0200
  • ef004a955b Merge branch 'devel' of gitlab.lip6.fr:vlsi-eda/coriolis into devel Jean-Paul Chaput 2021-05-31 00:07:15 +0200
  • 205a6877db More generic H-Tree support to accomodate the LS180 PLL internal clock. Jean-Paul Chaput 2021-05-31 00:02:23 +0200
  • 93ac03af07 repeat debug information when net direction changes some debug info is printed out if an OUTPUT net direction is reversed repeated the same code for an INPUT net Luke Kenneth Casson Leighton 2021-05-27 13:57:08 +0000
  • 5b6bc7c91b Add & fix GDS parser for PATH of type 4 (seen in the PLL). Jean-Paul Chaput 2021-05-25 15:08:57 +0200
  • 39231d5191 Allow to enable/disable minimal size checking in Contact CTOR. Jean-Paul Chaput 2021-05-25 14:56:07 +0200
  • 1bff74a56e Use simple pattern matching in Block._rgetInstance() (LKCL). Jean-Paul Chaput 2021-05-22 22:10:26 +0200
  • 3858461beb Added support for analog pad in Core2Chip & libresocio. Jean-Paul Chaput 2021-05-22 15:22:40 +0200
  • fd67ca6cda Correct handling of block orientation in block.py & macro.py. Jean-Paul Chaput 2021-05-22 15:21:26 +0200
  • d4c3cf7dbb More accurate antenna management in Anabatic. Jean-Paul Chaput 2021-05-22 15:14:32 +0200
  • dbdef9901f Separate the antenna max. WL into two distinct settings. Jean-Paul Chaput 2021-05-22 15:04:13 +0200
  • 4b2c120478 More comprehensive warning for offgrid shapes in GdsStream::xyToComponent(). Jean-Paul Chaput 2021-05-22 14:57:25 +0200
  • 90300eb651 Small typo in Cell::getComponentsUnder() Python wrapper. Jean-Paul Chaput 2021-05-22 14:54:36 +0200
  • 8ce16add53 Add a "forced halo" to diode clusters. Jean-Paul Chaput 2021-05-13 12:20:28 +0200
  • 7ffe75110b Fix, again, the save procedure in cumulus/plugins.chip & block. Jean-Paul Chaput 2021-05-12 12:12:52 +0200
  • c80e99c0a1 Create clusters for wire only chunks and add diodes if they are too long. Jean-Paul Chaput 2021-05-11 14:30:38 +0200
  • 7ad26f1a37 Ignore short overlaping same-net segments in realign stage. Jean-Paul Chaput 2021-05-11 14:19:27 +0200
  • ef8133b1c6 Correct renaming/save ordering in cumulus/plugins.chip.Chip.save() (again). Jean-Paul Chaput 2021-05-11 14:13:00 +0200
  • 28c8af27be Fix memory corruption due to the deletion of unused spare buffers. Jean-Paul Chaput 2021-05-11 14:11:43 +0200
  • 972787c81e Fix memory corruption in Etesian::Area, separate it's creation. Jean-Paul Chaput 2021-05-11 14:00:04 +0200
  • 079f4c2009 Fix unitialized stat structure in Vlsisapd, Path::mode() (valgrind). Jean-Paul Chaput 2021-05-11 13:46:53 +0200
  • c137c1ac5b Do not account self-segment in track cost calculation. Jean-Paul Chaput 2021-05-09 11:03:09 +0200
  • e50426a5bc Fix saving order in cumulus/chip.py to get right core instance name. Jean-Paul Chaput 2021-05-09 11:02:39 +0200
  • 1fb433d9ac Stop saving AP files when working in real mode. Jean-Paul Chaput 2021-05-04 19:31:34 +0200
  • bb5c99247a Complete rewrite of the diode insertion algorithm. Jean-Paul Chaput 2021-05-04 19:31:12 +0200
  • 44f716c4a2 Perform only one connexion to the power supplies and the corona ring. Jean-Paul Chaput 2021-04-28 23:38:32 +0200
  • e2d0188543 Fix net creation/lookup ordering in cumulus/core2chip (fuse vss & iovss). Jean-Paul Chaput 2021-04-28 14:24:47 +0200
  • 89a45180c1 In cumulus/core2chip, suppress "iovss", everything is connected to "vss". Jean-Paul Chaput 2021-04-28 13:35:48 +0200
  • dcfba9ef18 Export Catalog::State creation support to Python. Jean-Paul Chaput 2021-04-28 12:58:47 +0200
  • 39d8aa479e In cumulus/plugins.macro, check for the SRAM name in both upper/lower cases. Jean-Paul Chaput 2021-04-24 12:59:13 +0200
  • 440b71f727 In cumulus/plugins.block.Block.placeMacro(), move messages into trace mode. Jean-Paul Chaput 2021-04-24 12:58:51 +0200
  • 5cba995549 In cumulus/plugins.chip.powerplane, check for too-narrow power contacts. Jean-Paul Chaput 2021-04-24 12:58:22 +0200
  • 8d54a9cc29 In Etesian::Placement, reduce the number of warnings in case of misaligned block. Jean-Paul Chaput 2021-04-24 12:56:32 +0200
  • 496cc00304 In Katana, Adjust the moveUp cases in SegmentFsm/Manipulator. Jean-Paul Chaput 2021-04-24 12:56:16 +0200
  • 79f5b3db08 In AutoSegment::canMoveUp(), increase to 2 the added penalty under FlexLib. Jean-Paul Chaput 2021-04-24 12:55:47 +0200
  • decc4745d2 Add a RoutingLayerGauge.setType() and export to Python (finally unused). Jean-Paul Chaput 2021-04-24 12:55:17 +0200
  • 0640586cbc In CRL::VstDriver, name-mangle file names too with option UniquifyUpperCase. Jean-Paul Chaput 2021-04-22 15:14:06 +0200
  • 03a52977d3 Merge branch 'devel' of gitlab.lip6.fr:vlsi-eda/coriolis into devel Jean-Paul Chaput 2021-04-21 17:01:55 +0200
  • 37f311ac7d Don't remembers what thoses do, but don't want to loose them either. Jean-Paul Chaput 2021-04-21 17:00:48 +0200
  • 7ba68a0718 whoops, sorry... Luke Kenneth Casson Leighton 2021-04-21 14:30:58 +0000
  • 8932bcf7bc add BigVia.AllowAllExpand to all corona pads. this is already done elsewhere BigVia is used. no reason not to also use it in corona Luke Kenneth Casson Leighton 2021-04-21 14:07:29 +0000
  • d10961b585 Put the clock tree connecting wires farther apart from the corona border. Jean-Paul Chaput 2021-04-21 14:16:53 +0200
  • f2f5f687d0 Shrink macro block external pins. Jean-Paul Chaput 2021-04-21 14:16:26 +0200
  • f4514cecf3 Use Track::repair() to solve overlaps. Jean-Paul Chaput 2021-04-21 13:51:33 +0200
  • a05bd81bab Complete reorganization of where the routing stage is stored in Katana. Jean-Paul Chaput 2021-04-21 13:51:08 +0200
  • 493ed1ea11 In AutoSegment::canMoveUp(), adjust balance for FlexLib M2/M4. Jean-Paul Chaput 2021-04-21 13:49:41 +0200
  • ab908b8c44 Issue an early warning for offgrid coordinates in GdsParser. Jean-Paul Chaput 2021-04-19 14:29:23 +0200
  • cd4f797831 Export terminal of I/O pads at chip level. Jean-Paul Chaput 2021-04-19 14:26:29 +0200
  • 3b6b588a74 Manage pads for external components in CRL::GdsParser. Jean-Paul Chaput 2021-04-18 20:37:19 +0200
  • 7d1e1f8c44 Adjust again the interface of the SRAM block (METAL2 stick out more). Jean-Paul Chaput 2021-04-18 20:36:57 +0200
  • 2084a3bde2 Bad computation of the track axis for fixed in NetBuilderHV::_do_xG_1PinM2(). Jean-Paul Chaput 2021-04-18 20:36:44 +0200
  • 2019fa25d7 Fix crash when getting the free interval around a TrackSegment. Jean-Paul Chaput 2021-04-18 20:36:20 +0200
  • 444cc777e5 Fix topological bug in NetBuilderHV::_do_xG_1PinM2(). Jean-Paul Chaput 2021-04-17 13:03:15 +0200
  • 445f5161da Increase again blockages area over SRAMs blocks. Jean-Paul Chaput 2021-04-17 12:56:40 +0200
  • b0cfe8fc82 Fix bad spacing of the rightmost power lines (just a sign error). Jean-Paul Chaput 2021-04-17 12:54:49 +0200
  • aeb9d7d4e5 blif2vst.py naming of components needs to be munged https://gitlab.lip6.fr/vlsi-eda/coriolis/-/issues/36 Luke Kenneth Casson Leighton 2021-04-16 12:41:39 +0000
  • 628ff1ae06 correct direction of core-to-corona gpio pad connections for Net.Direction.IN cumulus/src/plugins/alpha/core2chip/core2chip.py Luke Kenneth Casson Leighton 2021-04-16 12:19:41 +0000
  • cc2137ec4f Check that the core is wide enough to accomodate at least one middle power line. Jean-Paul Chaput 2021-04-16 11:43:22 +0200
  • 9800c0ad3d Correct my botched patch on Etesian::HFNS buffer vs. net naming. Jean-Paul Chaput 2021-04-16 10:31:49 +0200
  • 8279e76070 In Etesian, set correct direction for buffereds HFNS nets. Jean-Paul Chaput 2021-04-16 00:05:04 +0200
  • 813d0860fd In Etesian::Placement, ensure that the tie in holes are pitcheds. Jean-Paul Chaput 2021-04-15 23:55:29 +0200