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Add VHDL "ref" keyword to CRL::NamingScheme. Cleanup BlifParser debug.

This commit is contained in:
Jean-Paul Chaput 2021-06-04 11:28:12 +02:00
parent 1d7a415e9f
commit 9b8ea64545
2 changed files with 1 additions and 2 deletions
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2
crlcore/src/ccore/blif/BlifParser.cpp
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@ -741,8 +741,6 @@ namespace {
// cerr << "sm0 plug:" << plug->getMasterNet()->getName() << " => net:" << net->getName() << endl;
// }
cerr << "plugNet=" << (void*)plugNet << endl;
cerr << "plug->getMasterNet()=" << (void*)(plug->getMasterNet()) << endl;
if (plugNet->isSupply() and not plug->getMasterNet()->isSupply()) {
ostringstream message;
message << "In " << instance << "\n "

1
crlcore/src/ccore/toolbox/NamingScheme.cpp
View File

@ -61,6 +61,7 @@ namespace CRL {
// VHDL reserved keywords (scalar).
if (loweredName == "in" ) return "in_v";
if (loweredName == "out" ) return "out_v";
if (loweredName == "ref" ) return "ref_v";
if (loweredName == "inout") return "inout_v";
if (loweredName == "true" ) return "bool_true";
if (loweredName == "false") return "bool_false";