More robust VST parser.
* Bug: In CRL Core, in VstParserGrammar.yy & VstParserScanner.ll, accurate
error message positions (file & line numbers).
When generating error message, we cannot pass char* on variables that
will be deallocated by the throw. So generate a string that will be
copied along with the exception. That problems explain numerous
core-dump when encountering syntaxes errors in the file.
This commit is contained in:
Jean-Paul Chaput
parent
978315c017
commit
8eac4b4b6f
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@ -1,46 +1,21 @@
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%{
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// This file is part of the Coriolis Project.
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// Copyright (C) Laboratoire LIP6 - Departement ASIM
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// Universite Pierre et Marie Curie
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// This file is part of the Coriolis Software.
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// Copyright (c) UPMC 2008-2014, All Rights Reserved
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//
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// Main contributors :
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// Christophe Alexandre <Christophe.Alexandre@lip6.fr>
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// Sophie Belloeil <Sophie.Belloeil@lip6.fr>
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// Hugo Clément <Hugo.Clement@lip6.fr>
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// Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
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// Damien Dupuis <Damien.Dupuis@lip6.fr>
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// Christian Masson <Christian.Masson@lip6.fr>
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// Marek Sroka <Marek.Sroka@lip6.fr>
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//
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// The Coriolis Project is free software; you can redistribute it
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// and/or modify it under the terms of the GNU General Public License
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// as published by the Free Software Foundation; either version 2 of
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// the License, or (at your option) any later version.
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//
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// The Coriolis Project is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty
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// of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with the Coriolis Project; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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//
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// License-Tag
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// Authors-Tag
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// ===================================================================
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//
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// This file is based on the Alliance VHDL parser written by
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// L.A. Tabusse, Vuong H.N., P. Bazargan-Sabet & D. Hommais.
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//
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// Yacc Rules for Alliance Structural VHDL.
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//
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// ===================================================================
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//
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// $Id$
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// +-----------------------------------------------------------------+
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// | C O R I O L I S |
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// | Alliance / Hurricane Interface |
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// | Yacc Grammar for Alliance Structural VHDL |
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// | |
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// | Author : Jean-Paul CHAPUT |
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// | E-mail : Jean-Paul.Chaput@asim.lip6.fr |
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// | =============================================================== |
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// | Yacc : "./VstParserGrammar.yy" |
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// | |
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// | This file is based on the Alliance VHDL parser written by |
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// | L.A. Tabusse, Vuong H.N., P. Bazargan-Sabet & D. Hommais |
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// +-----------------------------------------------------------------+
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#include <stdio.h>
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@ -49,9 +24,10 @@
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#include <sstream>
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#include <map>
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#include <vector>
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#include <queue>
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#include <deque>
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using namespace std;
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#include "hurricane/Warning.h"
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#include "hurricane/Net.h"
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#include "hurricane/Cell.h"
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#include "hurricane/Plug.h"
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@ -68,24 +44,30 @@ using namespace CRL;
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// Symbols from Flex which should be substituted.
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# define yyrestart VSTrestart
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# define yytext VSTtext
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# define yywrap VSTwrap
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# define yyin VSTin
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#define yyrestart VSTrestart
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#define yytext VSTtext
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#define yywrap VSTwrap
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#define yyin VSTin
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extern void ClearVstIdentifiers ();
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extern int yylex ();
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extern int yywrap ();
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extern void yyrestart ( FILE* );
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extern char* yytext;
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extern FILE* yyin;
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int vhdLineNumber = 1;
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namespace {
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int yyerror ( const char* message );
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} // Anonymous namespace.
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namespace Vst {
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extern void incVhdLineNumber ();
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extern void ClearIdentifiers ();
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class Constraint {
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private:
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@ -134,14 +116,15 @@ namespace {
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typedef map<Cell*,VectorMap> CellVectorMap;
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AllianceFramework* __framework;
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class YaccState {
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public:
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string _vhdFileName;
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int _vhdLineNumber;
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int _errorCount;
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int _maxErrors;
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queue<Name> _cellQueue;
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deque<Name> _cellQueue;
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Catalog::State* _state;
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Cell* _cell;
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Cell* _masterCell;
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@ -155,26 +138,39 @@ namespace {
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bool _firstPass;
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bool _behavioral;
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public:
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YaccState ()
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: _errorCount(0)
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, _maxErrors(10)
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, _cellQueue()
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, _state(NULL)
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, _cell(NULL)
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, _masterCell(NULL)
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, _instance(NULL)
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, _constraint()
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YaccState ( const string& vhdFileName )
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: _vhdFileName (vhdFileName)
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, _vhdLineNumber (1)
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, _errorCount (0)
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, _maxErrors (10)
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, _cellQueue ()
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, _state (NULL)
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, _cell (NULL)
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, _masterCell (NULL)
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, _instance (NULL)
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, _constraint ()
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, _identifiersList()
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, _cellVectorMap()
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, _instanceNets()
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, _masterNets()
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, _masterPort(true)
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, _firstPass(true)
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, _behavioral(false)
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, _cellVectorMap ()
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, _instanceNets ()
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, _masterNets ()
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, _masterPort (true)
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, _firstPass (true)
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, _behavioral (false)
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{ }
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bool pushCell ( Name );
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};
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bool YaccState::pushCell ( Name cellName )
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{
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for ( size_t i=0 ; i<_cellQueue.size(); ++i ) {
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if (_cellQueue[i] == cellName) return false;
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}
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_cellQueue.push_back( cellName );
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return true;
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}
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class YaccStateStack : public vector<YaccState*> {
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public:
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YaccState* operator->() { return back(); };
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@ -182,18 +178,15 @@ namespace {
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};
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YaccStateStack __ys;
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YaccStateStack states;
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AllianceFramework* framework;
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int yyerror ( const char* message );
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void VstError ( int code, const string& name );
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void Error ( int code, const string& name );
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Net* getNet ( Cell* cell, const string& name );
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void SetNetType ( Net* net );
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}
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} // Vst namespace.
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%}
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@ -388,7 +381,7 @@ entity_declaration
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Semicolon_ERR
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| ENTITY
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error
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{ VstError ( 2, "<no parameter>" ); }
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{ Vst::Error ( 2, "<no parameter>" ); }
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;
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.generic_clause.
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@ -426,8 +419,10 @@ formal_generic_element
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type_mark
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.constraint.
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generic_VarAsgn__expression
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{ __ys->_constraint.UnSet ();
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__ys->_identifiersList.clear ();
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{ if (not Vst::states->_firstPass) {
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Vst::states->_constraint.UnSet();
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Vst::states->_identifiersList.clear();
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}
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}
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| error
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;
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@ -451,7 +446,7 @@ constraint
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range
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: abstractlit
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direction
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abstractlit { __ys->_constraint.Set ( $1, $2, $3 ); }
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abstractlit { if (not Vst::states->_firstPass) Vst::states->_constraint.Set( $1, $2, $3 ); }
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;
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direction
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@ -473,7 +468,7 @@ port_clause
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| PORT
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error
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Semicolon_ERR
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{ VstError ( 3, "<no parameter>" ); }
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{ Vst::Error ( 3, "<no parameter>" ); }
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;
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formal_port_list
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@ -496,36 +491,36 @@ formal_port_element
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type_mark
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.constraint.
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.BUS.
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{ if ( !__ys->_firstPass ) {
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{ if (not Vst::states->_firstPass) {
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Net::Direction modeDirection = (Net::Direction::Code)$4;
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Net::Direction typeDirection = (Net::Direction::Code)$5;
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Net::Direction direction = (Net::Direction::Code)(modeDirection | typeDirection);
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for ( unsigned int i=0 ; i < __ys->_identifiersList.size() ; i++ ) {
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if ( __ys->_constraint.IsSet() ) {
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for ( unsigned int i=0 ; i < Vst::states->_identifiersList.size() ; i++ ) {
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if ( Vst::states->_constraint.IsSet() ) {
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int j;
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for ( __ys->_constraint.Init(j) ; __ys->_constraint.End(j) ; __ys->_constraint.Next(j) ) {
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for ( Vst::states->_constraint.Init(j) ; Vst::states->_constraint.End(j) ; Vst::states->_constraint.Next(j) ) {
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ostringstream name;
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name << *__ys->_identifiersList[i] << "(" << j << ")";
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Net* net = Net::create ( __ys->_cell, name.str() );
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name << *Vst::states->_identifiersList[i] << "(" << j << ")";
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Net* net = Net::create ( Vst::states->_cell, name.str() );
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net->setDirection ( direction );
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net->setExternal ( true );
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SetNetType ( net );
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__ys->_cellVectorMap[__ys->_cell][*__ys->_identifiersList[i]].push_back ( net );
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Vst::SetNetType ( net );
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Vst::states->_cellVectorMap[Vst::states->_cell][*Vst::states->_identifiersList[i]].push_back ( net );
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NetExtension::addPort ( net, name.str() );
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}
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} else {
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Net* net = Net::create ( __ys->_cell, *__ys->_identifiersList[i] );
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Net* net = Net::create ( Vst::states->_cell, *Vst::states->_identifiersList[i] );
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net->setDirection ( direction );
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net->setExternal ( true );
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SetNetType ( net );
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__ys->_cellVectorMap[__ys->_cell][*__ys->_identifiersList[i]].push_back ( net );
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NetExtension::addPort ( net, *__ys->_identifiersList[i] );
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Vst::SetNetType ( net );
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Vst::states->_cellVectorMap[Vst::states->_cell][*Vst::states->_identifiersList[i]].push_back ( net );
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NetExtension::addPort ( net, *Vst::states->_identifiersList[i] );
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}
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}
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}
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__ys->_constraint.UnSet ();
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__ys->_identifiersList.clear ();
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Vst::states->_constraint.UnSet ();
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Vst::states->_identifiersList.clear ();
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}
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}
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| error
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{ /* Reject tokens until the sync token Semicolon is found. */
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@ -534,35 +529,35 @@ formal_port_element
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} while ( (yychar != Semicolon) && (yychar != 0) );
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yyerrok;
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VstError ( 6, "<no parameter>" );
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Vst::Error ( 6, "<no parameter>" );
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}
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;
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architecture_body
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: ARCHITECTURE
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simple_name
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{ if ( ( __ys->_behavioral )
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|| ( __ys->_state->isFlattenLeaf() )
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|| ( __ys->_state->getDepth() <= 0 )
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{ if ( ( Vst::states->_behavioral )
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|| ( Vst::states->_state->isFlattenLeaf() )
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|| ( Vst::states->_state->getDepth() <= 0 )
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) YYACCEPT;
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}
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OF
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simple_name
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IS
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{ if ( __ys->_cell->getName() != *$5 ) VstError ( 1, *$5 ); }
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{ if ( Vst::states->_cell->getName() != *$5 ) Vst::Error ( 1, *$5 ); }
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architecture_declarative_part
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_BEGIN
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{ if ( __ys->_firstPass ) YYACCEPT; }
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{ /*if (Vst::states->_firstPass) YYACCEPT;*/ }
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architecture_statement_part
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END_ERR
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.simple_name.
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Semicolon_ERR
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{ if ( ( $13 != NULL ) && ( *$13 != *$2 ) )
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VstError ( 7, *$13 );
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Vst::Error ( 7, *$13 );
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}
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| ARCHITECTURE
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error
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{ VstError ( 8, "<no parameter>" ); }
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{ Vst::Error ( 8, "<no parameter>" ); }
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;
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architecture_declarative_part
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@ -580,7 +575,7 @@ block_declaration_item
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| component_declaration
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| error
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Semicolon_ERR
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{ VstError ( 9, "<no parameter>" ); }
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{ Vst::Error ( 9, "<no parameter>" ); }
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;
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signal_declaration
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@ -591,43 +586,43 @@ signal_declaration
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.constraint.
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.BUS.
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Semicolon_ERR
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{ if ( !__ys->_firstPass ) {
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{ if (not Vst::states->_firstPass) {
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Net::Direction direction = (Net::Direction::Code)$4;
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for ( unsigned int i=0 ; i < __ys->_identifiersList.size() ; i++ ) {
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if ( __ys->_constraint.IsSet() ) {
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for ( unsigned int i=0 ; i < Vst::states->_identifiersList.size() ; i++ ) {
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if ( Vst::states->_constraint.IsSet() ) {
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int j;
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for ( __ys->_constraint.Init(j) ; __ys->_constraint.End(j) ; __ys->_constraint.Next(j) ) {
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for ( Vst::states->_constraint.Init(j) ; Vst::states->_constraint.End(j) ; Vst::states->_constraint.Next(j) ) {
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ostringstream name;
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name << *__ys->_identifiersList[i] << "(" << j << ")";
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Net* net = Net::create ( __ys->_cell, name.str() );
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name << *Vst::states->_identifiersList[i] << "(" << j << ")";
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Net* net = Net::create ( Vst::states->_cell, name.str() );
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net->setDirection ( direction );
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net->setExternal ( false );
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SetNetType ( net );
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__ys->_cellVectorMap[__ys->_cell][*__ys->_identifiersList[i]].push_back ( net );
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Vst::SetNetType ( net );
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Vst::states->_cellVectorMap[Vst::states->_cell][*Vst::states->_identifiersList[i]].push_back ( net );
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}
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} else {
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Net* net = Net::create ( __ys->_cell, *__ys->_identifiersList[i] );
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Net* net = Net::create ( Vst::states->_cell, *Vst::states->_identifiersList[i] );
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net->setDirection ( direction );
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net->setExternal ( false );
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SetNetType ( net );
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__ys->_cellVectorMap[__ys->_cell][*__ys->_identifiersList[i]].push_back ( net );
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Vst::SetNetType ( net );
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Vst::states->_cellVectorMap[Vst::states->_cell][*Vst::states->_identifiersList[i]].push_back ( net );
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}
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}
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}
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__ys->_constraint.UnSet ();
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__ys->_identifiersList.clear ();
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Vst::states->_constraint.UnSet ();
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Vst::states->_identifiersList.clear ();
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}
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;
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component_declaration
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: COMPONENT
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Identifier
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{ if ( __ys->_firstPass ) {
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if ( !__framework->getCell(*$2,Catalog::State::Views|Catalog::State::InMemory) )
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__ys->_cellQueue.push ( *$2 );
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{ if (Vst::states->_firstPass) {
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if (not Vst::framework->getCell(*$2,Catalog::State::Views|Catalog::State::InMemory))
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Vst::states->pushCell( *$2 );
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} else {
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__ys->_masterCell = __framework->getCell ( *$2, Catalog::State::Views );
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Vst::states->_masterCell = Vst::framework->getCell ( *$2, Catalog::State::Views );
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}
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}
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.generic_clause.
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@ -666,25 +661,25 @@ local_port_element
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type_mark
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.constraint.
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.BUS.
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{ if ( !__ys->_firstPass ) {
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for ( unsigned int i=0 ; i < __ys->_identifiersList.size() ; i++ ) {
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if ( __ys->_constraint.IsSet() ) {
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{ if (not Vst::states->_firstPass) {
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for ( unsigned int i=0 ; i < Vst::states->_identifiersList.size() ; i++ ) {
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if ( Vst::states->_constraint.IsSet() ) {
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int j;
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for ( __ys->_constraint.Init(j) ; __ys->_constraint.End(j) ; __ys->_constraint.Next(j) ) {
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for ( Vst::states->_constraint.Init(j) ; Vst::states->_constraint.End(j) ; Vst::states->_constraint.Next(j) ) {
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ostringstream name;
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name << *__ys->_identifiersList[i] << "(" << j << ")";
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Net* net = getNet ( __ys->_masterCell, name.str() );
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__ys->_cellVectorMap[__ys->_masterCell][*__ys->_identifiersList[i]].push_back ( net );
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name << *Vst::states->_identifiersList[i] << "(" << j << ")";
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Net* net = Vst::getNet ( Vst::states->_masterCell, name.str() );
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Vst::states->_cellVectorMap[Vst::states->_masterCell][*Vst::states->_identifiersList[i]].push_back ( net );
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}
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} else {
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Net* net = getNet ( __ys->_masterCell, *__ys->_identifiersList[i] );
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__ys->_cellVectorMap[__ys->_masterCell][*__ys->_identifiersList[i]].push_back ( net );
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Net* net = Vst::getNet ( Vst::states->_masterCell, *Vst::states->_identifiersList[i] );
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Vst::states->_cellVectorMap[Vst::states->_masterCell][*Vst::states->_identifiersList[i]].push_back ( net );
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}
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}
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}
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__ys->_constraint.UnSet ();
|
||||
__ys->_identifiersList.clear ();
|
||||
Vst::states->_constraint.UnSet ();
|
||||
Vst::states->_identifiersList.clear ();
|
||||
}
|
||||
| error
|
||||
{ /* Reject tokens until the sync token Semicolon is found. */
|
||||
|
|
@ -693,7 +688,7 @@ local_port_element
|
|||
} while ( (yychar != Semicolon) && (yychar != 0) );
|
||||
yyerrok;
|
||||
|
||||
VstError ( 6, "<no parameter>" );
|
||||
Vst::Error ( 6, "<no parameter>" );
|
||||
}
|
||||
;
|
||||
|
||||
|
|
@ -711,21 +706,36 @@ concurrent_statement
|
|||
: component_instantiation_statement
|
||||
| error
|
||||
Semicolon_ERR
|
||||
{ VstError (18, "<no parameter>"); }
|
||||
{ Vst::Error (18, "<no parameter>"); }
|
||||
;
|
||||
|
||||
component_instantiation_statement
|
||||
: a_label
|
||||
simple_name
|
||||
{ __ys->_masterCell = __framework->getCell ( *$2, Catalog::State::Views|Catalog::State::InMemory );
|
||||
if ( !__ys->_masterCell )
|
||||
throw Error ( "CParsVst(), Line %d:\n"
|
||||
" Model cell %s of instance %s has not been defined "
|
||||
"in the component list."
|
||||
, vhdLineNumber, *$2->c_str(), *$1->c_str()
|
||||
);
|
||||
__ys->_instance = Instance::create ( __ys->_cell, *$1, __ys->_masterCell );
|
||||
__ys->_cell->setTerminal ( false );
|
||||
{ if (not Vst::states->_firstPass) {
|
||||
Vst::states->_masterCell = Vst::framework->getCell( *$2, Catalog::State::Views|Catalog::State::InMemory );
|
||||
if (not Vst::states->_masterCell) {
|
||||
ostringstream message;
|
||||
message << "CParsVst() VHDL Parser - File:<" << Vst::states->_vhdFileName
|
||||
<< "> Line:" << Vst::states->_vhdLineNumber << "\n"
|
||||
<< " Model cell " << *$2 << " of instance "
|
||||
<< *$1 << " has not been defined in the component list.";
|
||||
throw Error( message.str() );
|
||||
}
|
||||
Vst::states->_instance = Instance::create( Vst::states->_cell, *$1, Vst::states->_masterCell );
|
||||
Vst::states->_cell->setTerminal( false );
|
||||
} else {
|
||||
if (not Vst::framework->getCell(*$2,Catalog::State::Views|Catalog::State::InMemory)) {
|
||||
if (Vst::states->pushCell(*$2)) {
|
||||
ostringstream message;
|
||||
message << "CParsVst() VHDL Parser - File:<" << Vst::states->_vhdFileName
|
||||
<< "> Line:" << Vst::states->_vhdLineNumber << "\n"
|
||||
<< " Model cell " << *$2 << " of instance "
|
||||
<< *$1 << " has not been defined in the component list.";
|
||||
cerr << Warning( message.str() );
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
.generic_map_aspect.
|
||||
.port_map_aspect.
|
||||
|
|
@ -891,28 +901,36 @@ association_list
|
|||
association_element
|
||||
: formal_port_name
|
||||
Arrow
|
||||
{ __ys->_masterPort = false; }
|
||||
{ if (not Vst::states->_firstPass) Vst::states->_masterPort = false; }
|
||||
actual_port_name
|
||||
{ if ( __ys->_masterNets.size() != __ys->_instanceNets.size() )
|
||||
throw Error ( "CParsVst(), line %d:\n"
|
||||
" Port map assignment discrepency."
|
||||
, vhdLineNumber
|
||||
);
|
||||
|
||||
for ( unsigned int i=0 ; i < __ys->_masterNets.size() ; i++ )
|
||||
if ( not __ys->_masterNets[i]->isGlobal()
|
||||
or (__ys->_masterNets[i]->getName() != __ys->_instanceNets[i]->getName()) )
|
||||
__ys->_instance->getPlug ( __ys->_masterNets[i] )->setNet ( __ys->_instanceNets[i] );
|
||||
|
||||
__ys->_masterPort = true;
|
||||
__ys->_masterNets.clear ();
|
||||
__ys->_instanceNets.clear ();
|
||||
{ if (not Vst::states->_firstPass) {
|
||||
if ( Vst::states->_masterNets.size() != Vst::states->_instanceNets.size() ) {
|
||||
ostringstream message;
|
||||
message << "CParsVst() VHDL Parser - File:<" << Vst::states->_vhdFileName.c_str()
|
||||
<< "> Line:" << Vst::states->_vhdLineNumber << "\n"
|
||||
<< " Port map assignment discrepency "
|
||||
<< "instance:" << Vst::states->_instanceNets.size()
|
||||
<< " vs. model:" << Vst::states->_masterNets.size();
|
||||
throw Error( message.str() );
|
||||
}
|
||||
|
||||
for ( unsigned int i=0 ; i < Vst::states->_masterNets.size() ; i++ )
|
||||
if ( not Vst::states->_masterNets[i]->isGlobal()
|
||||
or (Vst::states->_masterNets[i]->getName() != Vst::states->_instanceNets[i]->getName()) )
|
||||
Vst::states->_instance->getPlug ( Vst::states->_masterNets[i] )->setNet ( Vst::states->_instanceNets[i] );
|
||||
|
||||
Vst::states->_masterPort = true;
|
||||
Vst::states->_masterNets.clear ();
|
||||
Vst::states->_instanceNets.clear ();
|
||||
}
|
||||
}
|
||||
| actual_port_name
|
||||
{ throw Error ( "CParsVst(), line %d:\n"
|
||||
" While processing %s: implicit connexions are not allowed.\n"
|
||||
, vhdLineNumber, getString(__ys->_instance->getName()).c_str()
|
||||
);
|
||||
{ ostringstream message;
|
||||
message << "CParsVst() VHDL Parser - File<" << Vst::states->_vhdFileName
|
||||
<< ">, Line:" << Vst::states->_vhdLineNumber << "\n"
|
||||
<< " While processing " << Vst::states->_instance->getName()
|
||||
<< ": implicit connexions are not allowed.\n";
|
||||
throw Error( message.str() );
|
||||
}
|
||||
| error
|
||||
{ /* Reject tokens until the sync token Comma is found. */
|
||||
|
|
@ -921,7 +939,7 @@ association_element
|
|||
} while ( (yychar != Comma) && (yychar != 0) );
|
||||
yyerrok;
|
||||
|
||||
VstError ( 31, "<no parameter>" );
|
||||
Vst::Error ( 31, "<no parameter>" );
|
||||
}
|
||||
;
|
||||
|
||||
|
|
@ -935,15 +953,17 @@ actual_port_name
|
|||
|
||||
name
|
||||
: simple_name
|
||||
{ if ( __ys->_masterPort ) {
|
||||
PinVector& nets = __ys->_cellVectorMap[__ys->_masterCell][*$1];
|
||||
for ( unsigned int i=0 ; i < nets.size() ; i++ ) {
|
||||
__ys->_masterNets.push_back ( nets[i] );
|
||||
}
|
||||
} else {
|
||||
PinVector& nets = __ys->_cellVectorMap[__ys->_cell][*$1];
|
||||
for ( unsigned int i=0 ; i < nets.size() ; i++ ) {
|
||||
__ys->_instanceNets.push_back ( nets[i] );
|
||||
{ if (not Vst::states->_firstPass) {
|
||||
if ( Vst::states->_masterPort ) {
|
||||
Vst::PinVector& nets = Vst::states->_cellVectorMap[Vst::states->_masterCell][*$1];
|
||||
for ( unsigned int i=0 ; i < nets.size() ; i++ ) {
|
||||
Vst::states->_masterNets.push_back ( nets[i] );
|
||||
}
|
||||
} else {
|
||||
Vst::PinVector& nets = Vst::states->_cellVectorMap[Vst::states->_cell][*$1];
|
||||
for ( unsigned int i=0 ; i < nets.size() ; i++ ) {
|
||||
Vst::states->_instanceNets.push_back ( nets[i] );
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -956,26 +976,30 @@ indexed_name
|
|||
LeftParen
|
||||
abstractlit
|
||||
RightParen_ERR
|
||||
{ ostringstream name;
|
||||
name << *$1 << "(" << $3 << ")";
|
||||
if ( __ys->_masterPort )
|
||||
__ys->_masterNets.push_back ( getNet(__ys->_masterCell,name.str()) );
|
||||
else
|
||||
__ys->_instanceNets.push_back ( getNet(__ys->_cell,name.str()) );
|
||||
{ if (not Vst::states->_firstPass) {
|
||||
ostringstream name;
|
||||
name << *$1 << "(" << $3 << ")";
|
||||
if ( Vst::states->_masterPort )
|
||||
Vst::states->_masterNets.push_back ( Vst::getNet(Vst::states->_masterCell,name.str()) );
|
||||
else
|
||||
Vst::states->_instanceNets.push_back ( Vst::getNet(Vst::states->_cell,name.str()) );
|
||||
}
|
||||
}
|
||||
;
|
||||
|
||||
slice_name
|
||||
: simple_name
|
||||
constraint
|
||||
{ int j;
|
||||
for ( __ys->_constraint.Init(j) ; __ys->_constraint.End(j) ; __ys->_constraint.Next(j) ) {
|
||||
ostringstream name;
|
||||
name << *$1 << "(" << j << ")";
|
||||
if ( __ys->_masterPort )
|
||||
__ys->_masterNets.push_back ( getNet(__ys->_masterCell,name.str()) );
|
||||
else
|
||||
__ys->_instanceNets.push_back ( getNet(__ys->_cell,name.str()) );
|
||||
{ if (not Vst::states->_firstPass) {
|
||||
int j;
|
||||
for ( Vst::states->_constraint.Init(j) ; Vst::states->_constraint.End(j) ; Vst::states->_constraint.Next(j) ) {
|
||||
ostringstream name;
|
||||
name << *$1 << "(" << j << ")";
|
||||
if ( Vst::states->_masterPort )
|
||||
Vst::states->_masterNets.push_back ( Vst::getNet(Vst::states->_masterCell,name.str()) );
|
||||
else
|
||||
Vst::states->_instanceNets.push_back ( Vst::getNet(Vst::states->_cell,name.str()) );
|
||||
}
|
||||
}
|
||||
}
|
||||
;
|
||||
|
|
@ -1072,7 +1096,7 @@ type_mark
|
|||
;
|
||||
|
||||
identifier_list
|
||||
: Identifier { __ys->_identifiersList.push_back ( $1 ); }
|
||||
: Identifier { if (not Vst::states->_firstPass) Vst::states->_identifiersList.push_back( $1 ); }
|
||||
...identifier..
|
||||
;
|
||||
|
||||
|
|
@ -1080,7 +1104,7 @@ identifier_list
|
|||
: /*empty*/
|
||||
| ...identifier..
|
||||
Comma
|
||||
Identifier { __ys->_identifiersList.push_back ( $3 ); }
|
||||
Identifier { if (not Vst::states->_firstPass) Vst::states->_identifiersList.push_back( $3 ); }
|
||||
;
|
||||
|
||||
a_label
|
||||
|
|
@ -1127,32 +1151,44 @@ namespace {
|
|||
|
||||
int yyerror ( const char* message )
|
||||
{
|
||||
throw Error ( "CParsVst():\n %s before %s at line %d.\n"
|
||||
, message, yytext, vhdLineNumber );
|
||||
ostringstream formatted;
|
||||
formatted << "CParsVst() - VHDL Parser, File:<" << Vst::states->_vhdFileName
|
||||
<< ">, Line:" << Vst::states->_vhdLineNumber << "\n "
|
||||
<< message << " before " << yytext << ".\n";
|
||||
throw Hurricane::Error( formatted.str() );
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
} // Anonymous namespace.
|
||||
|
||||
|
||||
namespace Vst {
|
||||
|
||||
|
||||
void incVhdLineNumber ()
|
||||
{ ++states->_vhdLineNumber; }
|
||||
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
// Function : "VstError()".
|
||||
// Function : "Vst::Error()".
|
||||
//
|
||||
// Manage errors from wich we can recover and continue a little
|
||||
// while.
|
||||
|
||||
void VstError ( int code, const string& name )
|
||||
void Error ( int code, const string& name )
|
||||
{
|
||||
__ys->_errorCount++;
|
||||
states->_errorCount++;
|
||||
|
||||
if ( __ys->_errorCount >= __ys->_maxErrors )
|
||||
throw Error ( "CParsVst(): Too many errors occured.\n" );
|
||||
if ( states->_errorCount >= states->_maxErrors )
|
||||
throw Hurricane::Error ( "CParsVst() VHDL Parser, Too many errors occured.\n" );
|
||||
|
||||
if ( code < 100 )
|
||||
cerr << "[ERROR] CParsVst(): Code " << code << " line " << vhdLineNumber << " :\n ";
|
||||
cerr << "[ERROR] CParsVst() VHDL Parser, File:<" << states->_vhdFileName
|
||||
<< ">, Line:%d" << states->_vhdLineNumber << " Code:" << code << " :\n ";
|
||||
else {
|
||||
if (code < 200)
|
||||
cerr << "[ERROR] CParsVst(): Code " << code << " :\n ";
|
||||
cerr << "[ERROR] CParsVst() VHDL Parser, Code:" << code << " :\n ";
|
||||
}
|
||||
|
||||
switch ( code ) {
|
||||
|
|
@ -1183,13 +1219,11 @@ namespace {
|
|||
case 76: cerr << "Instance \"" << name << "\"mismatch with model." << endl; break;
|
||||
default: cerr << "Syntax error." << endl; break;
|
||||
case 200:
|
||||
throw Error ( "Error(s) occured.\n" );
|
||||
throw Hurricane::Error ( "Error(s) occured.\n" );
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
// Function : "getNet()".
|
||||
|
||||
|
|
@ -1197,39 +1231,38 @@ namespace {
|
|||
{
|
||||
Net* net = cell->getNet ( Name(name) );
|
||||
if ( !net ) {
|
||||
throw Error ( "CParsVst(), line %d:\n"
|
||||
" No net \"%s\" in cell \"%s\".\n"
|
||||
, vhdLineNumber
|
||||
, name.c_str()
|
||||
, getString(cell->getName()).c_str()
|
||||
);
|
||||
ostringstream message;
|
||||
message << "CParsVst() VHDL Parser, File:<" << states->_vhdFileName
|
||||
<< "> Line:" << states->_vhdLineNumber
|
||||
<< "\n"
|
||||
<< " No net \"" << name
|
||||
<< "\" in cell \"" << cell->getName() << "\".\n";
|
||||
throw Hurricane::Error( message.str() );
|
||||
}
|
||||
|
||||
return net;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
// Function : "SetNetType()".
|
||||
|
||||
void SetNetType ( Net* net )
|
||||
{
|
||||
if ( __framework->isPOWER(net->getName()) ) {
|
||||
if ( framework->isPOWER(net->getName()) ) {
|
||||
net->setType ( Net::Type::POWER );
|
||||
net->setGlobal ( true );
|
||||
} else if ( __framework->isGROUND(net->getName()) ) {
|
||||
} else if ( framework->isGROUND(net->getName()) ) {
|
||||
net->setType ( Net::Type::GROUND );
|
||||
net->setGlobal ( true );
|
||||
} else if ( __framework->isCLOCK(net->getName()) ) {
|
||||
} else if ( framework->isCLOCK(net->getName()) ) {
|
||||
net->setType ( Net::Type::CLOCK );
|
||||
} else
|
||||
net->setType ( Net::Type::LOGICAL );
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
} // Vst namespace.
|
||||
|
||||
|
||||
|
||||
|
|
@ -1242,27 +1275,27 @@ namespace CRL {
|
|||
|
||||
void vstParser ( const string cellPath, Cell *cell )
|
||||
{
|
||||
cmess2 << " " << tab << "+ " << cellPath << endl; tab++;
|
||||
cmess2 << " " << tab << "+ " << cellPath << " (childs)" << endl; tab++;
|
||||
|
||||
static bool firstCall = true;
|
||||
if ( firstCall ) {
|
||||
firstCall = false;
|
||||
__framework = AllianceFramework::get ();
|
||||
firstCall = false;
|
||||
Vst::framework = AllianceFramework::get ();
|
||||
}
|
||||
|
||||
__ys.push_back ( new YaccState() );
|
||||
Vst::states.push_back ( new Vst::YaccState(cellPath) );
|
||||
|
||||
if ( ( cellPath.size() > 4 ) && ( !cellPath.compare(cellPath.size()-4,4,".vbe") ) )
|
||||
__ys->_behavioral = true;
|
||||
Vst::states->_behavioral = true;
|
||||
|
||||
CatalogProperty *sprop =
|
||||
(CatalogProperty*)cell->getProperty ( CatalogProperty::getPropertyName() );
|
||||
if ( sprop == NULL )
|
||||
throw Error ( "Missing CatalogProperty in cell %s.\n" , getString(cell->getName()).c_str() );
|
||||
|
||||
__ys->_state = sprop->getState ();
|
||||
__ys->_state->setLogical ( true );
|
||||
__ys->_cell = cell;
|
||||
Vst::states->_state = sprop->getState ();
|
||||
Vst::states->_state->setLogical ( true );
|
||||
Vst::states->_cell = cell;
|
||||
|
||||
IoFile ccell ( cellPath );
|
||||
ccell.open ( "r" );
|
||||
|
|
@ -1270,24 +1303,22 @@ void vstParser ( const string cellPath, Cell *cell )
|
|||
if ( !firstCall ) yyrestart ( VSTin );
|
||||
yyparse ();
|
||||
|
||||
bool hasInstances = false;
|
||||
while ( !__ys->_cellQueue.empty() ) {
|
||||
hasInstances = true;
|
||||
if ( !__framework->getCell ( getString(__ys->_cellQueue.front())
|
||||
, Catalog::State::Views
|
||||
, __ys->_state->getDepth()-1) ) {
|
||||
throw Error ( "CParsVst():\n"
|
||||
" Unable to find cell \"%s\", please check your <.environment.alliance.xml>.\n"
|
||||
, getString(__ys->_cellQueue.front()).c_str()
|
||||
while ( !Vst::states->_cellQueue.empty() ) {
|
||||
if ( !Vst::framework->getCell ( getString(Vst::states->_cellQueue.front())
|
||||
, Catalog::State::Views
|
||||
, Vst::states->_state->getDepth()-1) ) {
|
||||
throw Error ( "CParsVst() VHDL Parser:\n"
|
||||
" Unable to find cell \"%s\", please check your <.coriolis2/settings.py>.\n"
|
||||
, getString(Vst::states->_cellQueue.front()).c_str()
|
||||
);
|
||||
}
|
||||
__ys->_cellQueue.pop ();
|
||||
Vst::states->_cellQueue.pop_front();
|
||||
}
|
||||
|
||||
if ( hasInstances ) cmess2 << " " << --tab << "+ " << cellPath << endl;
|
||||
else --tab;
|
||||
cmess2 << " " << --tab << "+ " << cellPath << " (loading)" << endl;
|
||||
|
||||
__ys->_firstPass = false;
|
||||
Vst::states->_firstPass = false;
|
||||
Vst::states->_vhdLineNumber = 1;
|
||||
ccell.close ();
|
||||
ccell.open ( "r" );
|
||||
yyin = ccell.getFile ();
|
||||
|
|
@ -1295,9 +1326,14 @@ void vstParser ( const string cellPath, Cell *cell )
|
|||
UpdateSession::open ();
|
||||
yyparse ();
|
||||
UpdateSession::close ();
|
||||
ClearVstIdentifiers ();
|
||||
|
||||
__ys.pop_back();
|
||||
forEach ( Net*, inet, Vst::states->_cell->getNets() ) {
|
||||
cerr << *inet << endl;
|
||||
}
|
||||
|
||||
Vst::ClearIdentifiers ();
|
||||
Vst::states.pop_back();
|
||||
|
||||
|
||||
ccell.close ();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,47 +3,25 @@
|
|||
|
||||
%{
|
||||
|
||||
// This file is part of the Coriolis Project.
|
||||
// Copyright (C) Laboratoire LIP6 - Departement ASIM
|
||||
// Universite Pierre et Marie Curie
|
||||
// This file is part of the Coriolis Software.
|
||||
// Copyright (c) UPMC 2008-2014, All Rights Reserved
|
||||
//
|
||||
// Main contributors :
|
||||
// Christophe Alexandre <Christophe.Alexandre@lip6.fr>
|
||||
// Sophie Belloeil <Sophie.Belloeil@lip6.fr>
|
||||
// Hugo Clément <Hugo.Clement@lip6.fr>
|
||||
// Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
|
||||
// Damien Dupuis <Damien.Dupuis@lip6.fr>
|
||||
// Christian Masson <Christian.Masson@lip6.fr>
|
||||
// Marek Sroka <Marek.Sroka@lip6.fr>
|
||||
//
|
||||
// The Coriolis Project is free software; you can redistribute it
|
||||
// and/or modify it under the terms of the GNU General Public License
|
||||
// as published by the Free Software Foundation; either version 2 of
|
||||
// the License, or (at your option) any later version.
|
||||
//
|
||||
// The Coriolis Project is distributed in the hope that it will be
|
||||
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty
|
||||
// of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with the Coriolis Project; if not, write to the Free Software
|
||||
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
// USA
|
||||
//
|
||||
// License-Tag
|
||||
// Authors-Tag
|
||||
// ===================================================================
|
||||
//
|
||||
// This file is based on the Alliance VHDL parser written by
|
||||
// L.A. Tabusse & Vuong H.N. (1992)
|
||||
//
|
||||
// Lexical VHDL Analyser. Please refer to the IEEE Standard VHDL LRM
|
||||
// Chapter 13 : Lexical Elements.
|
||||
//
|
||||
// ===================================================================
|
||||
//
|
||||
// $Id: CParsVstScan.ll,v 1.2 2006/02/19 00:52:44 jpc Exp $
|
||||
// +-----------------------------------------------------------------+
|
||||
// | C O R I O L I S |
|
||||
// | Alliance / Hurricane Interface |
|
||||
// | |
|
||||
// | Author : Jean-Paul CHAPUT |
|
||||
// | E-mail : Jean-Paul.Chaput@asim.lip6.fr |
|
||||
// | =============================================================== |
|
||||
// | Lex : "./VstParserScanner.ll" |
|
||||
// | |
|
||||
// | This file is based on the Alliance VHDL parser written by |
|
||||
// | L.A. Tabusse, Vuong H.N., P. Bazargan-Sabet & D. Hommais |
|
||||
// | |
|
||||
// | Lexical VHDL Analyser. Please refer to the IEEE Standard VHDL |
|
||||
// | LRM Chapter 13 : Lexical Elements. |
|
||||
// +-----------------------------------------------------------------+
|
||||
|
||||
|
||||
# include <string.h>
|
||||
|
||||
|
|
@ -56,8 +34,14 @@ using namespace std;
|
|||
|
||||
# include "VstParserGrammar.hpp"
|
||||
|
||||
extern int vhdLineNumber;
|
||||
extern void ClearVstIdentifiers ();
|
||||
|
||||
|
||||
namespace Vst {
|
||||
|
||||
extern void ClearIdentifiers ();
|
||||
extern void incVhdLineNumber ();
|
||||
|
||||
}
|
||||
|
||||
|
||||
namespace {
|
||||
|
|
@ -307,8 +291,8 @@ base_specifier (B|b|O|o|X|x)
|
|||
return BitStringLit;
|
||||
}
|
||||
|
||||
\n { /* end of line */ vhdLineNumber++; }
|
||||
\-\-.*$ { /* comment : skip them */ vhdLineNumber++; }
|
||||
\n { /* end of line */ Vst::incVhdLineNumber(); }
|
||||
\-\-.*$ { /* comment : skip them */ }
|
||||
. { return *yytext; }
|
||||
|
||||
|
||||
|
|
@ -318,22 +302,26 @@ base_specifier (B|b|O|o|X|x)
|
|||
int yywrap () { return 1; }
|
||||
|
||||
|
||||
void ClearVstIdentifiers ()
|
||||
{
|
||||
identifiers.clear ();
|
||||
}
|
||||
namespace Vst {
|
||||
|
||||
|
||||
void ClearIdentifiers ()
|
||||
{ identifiers.clear (); }
|
||||
|
||||
|
||||
} // Vst namespace.
|
||||
|
||||
|
||||
namespace {
|
||||
|
||||
|
||||
char* lower ( char* str )
|
||||
{
|
||||
for ( char* ptr = str; *ptr != '\0' ; ptr++ )
|
||||
*ptr = (char)tolower ( *ptr );
|
||||
|
||||
return str;
|
||||
}
|
||||
char* lower ( char* str )
|
||||
{
|
||||
for ( char* ptr = str; *ptr != '\0' ; ptr++ )
|
||||
*ptr = (char)tolower ( *ptr );
|
||||
|
||||
return str;
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
} // Anonymous namespace.
|
||||
|
|
|
|||
Loading…
Reference in New Issue