Commit Graph

80 Commits

Author SHA1 Message Date
Liviu Ionescu 08a814686d target/riscv: add semihosting support
- use the semihosting_common code
- to enable it, use the same commands as for arm

Signed-off-by: Liviu Ionescu <ilg@livius.net>
2018-06-12 18:21:01 +03:00
Tim Newsome 69a426038d
Enforce OpenOCD style guide. (#239)
* Enforce OpenOCD style guide.

Change-Id: I579a9f54ed22a774bf52f6aa5bc13bcbd2e82cd8

* Fail if `git diff` fails

Change-Id: I57256b0a24247f6123cb0e25a89c1b59867cb3f9

* Maybe every line gets its own shell?

Change-Id: I1a6f83e9f3d7cfd39f8933f0dba13c3cf76f71f6

* Maybe this will error properly.

Change-Id: I50803cfc229e61158569fb6b609195f7191ecac9

* Take different approach than merge-base

Change-Id: I345cbc4eecc4755c7127e8e36e403f7b727010b1

* Fix style issues.

Change-Id: I90e71f710858524812d0ab160b25c486b7b099e7
2018-04-18 13:11:08 -07:00
Tim Newsome 6030644a9d Track misa per-hart even in -rtos mode
This works around some side effects of the -rtos hack, namely that we
were unable to set hardware breakpoints on harts whose misa differed
from the first one. There may be other bugs like this one lurking
elsewhere. The only proper solution is for gdb to have a better user
interface when talking to a server that exposes multiple targets, but
that's a very big project.

This fixes #194.

Change-Id: I81aedddeaa922d220e936730e9c731545953ae21
2018-04-03 15:12:19 -07:00
Tim Newsome 553a63808c Fix some niggles found by clang's static analysis.
Change-Id: Id476227e1bd02e067f0cc4da9bc7ffb3d9d30535
2018-01-23 15:16:23 -08:00
Megan Wachs 6f9585068f
Merge pull request #172 from riscv/dbus_read_comment
Add a comment in dbus_read
2018-01-10 15:30:56 -08:00
Tim Newsome fd506fa839 Propagate register read errors.
Change-Id: Idda111377873a2236b5b91e4ffdabd2be384b47a
2018-01-08 11:53:02 -08:00
Tim Newsome 11e51af3b1
Merge pull request #173 from riscv/warn_names
Use register names instead of numbers in warnings
2018-01-05 13:07:08 -08:00
Tim Newsome 097d62d159 Make delay update messages debug instead of info.
They confuse users otherwise.

Change-Id: I3bc491352f5384e36c54696a0ecbf11ac623dd83
2018-01-04 13:36:53 -08:00
Megan Wachs 33aad3524b
Add a comment in dbus_read
This just comments the current behavior
2018-01-04 13:27:35 -08:00
Tim Newsome 07e19e17cb Use register names instead of numbers in warnings
Change-Id: Ie2295d30fd9dfeb7590f5e34d572497a93a3ce7b
2018-01-04 13:27:18 -08:00
Tim Newsome 365c79c3ff Get rid of abort() calls.
Also changed a few asserts that could trigger due to broken hardware.

Fixes Issue #142.

Change-Id: Ia2b99baa82f30ebcb2fd7e4902f0e67046ce4ed2
2017-12-27 13:45:50 -08:00
Tim Newsome d942bce996 Conform to OpenOCD style guide.
Change-Id: I2b23ac79639ed40e9d59db5c52ea2196df0349bc
2017-12-26 11:38:11 -08:00
Tim Newsome f341db9f72 WIP xml register for 0.11.
On HiFive1, FPRs show up with no name, and misa is 0x1105 instead of
0x40001105.

Change-Id: I4ee223c905ad7d860147014e7b6394668658c6ea
2017-12-19 10:41:48 -08:00
Tim Newsome 26a54452d2 Fix register names.
Use the ABI ones for every register that we have one for.

Change-Id: I2a993abff416d2652dbe026b3fb498e144a5006f
2017-12-19 10:41:48 -08:00
Tim Newsome 24658db50e Fix compile warnings.
Partly fixes #124.

Change-Id: I3a7fd65c643e40b142709806cb9fb4cc62bb955f
2017-10-04 16:02:30 -07:00
Tim Newsome abe7eba25a Merge pull request #118 from riscv/priv
Fix priv access
2017-10-04 12:52:21 -07:00
Liviu Ionescu 728a617bd4 target/riscv: Silence -Werror=return-type
- clang compains about the functions not returning a value
2017-10-03 00:17:57 +03:00
Tim Newsome 6795270a8e Make priv readable in 0.11. 2017-09-30 13:31:57 -07:00
Tim Newsome 1083352576 Share register numbers between 0.11 and 0.13. 2017-09-30 13:13:03 -07:00
Megan Wachs 879c274cb9 riscv: Add commands for setting timeouts 2017-08-15 15:59:40 -07:00
Tim Newsome d60dbd60e8 Share trigger code between 0.11 and 0.13 code.
The actual implementation of triggers didn't change between those two
versions, so there's no need to duplicate the code.

In the process, I also fixed a minor multicore bug where tselect didn't
always get written on all harts.
2017-07-12 19:54:40 -07:00
Tim Newsome 4072fa493b Disable debugger-set triggers on connect
When first connecting to a target, have the debugger disable any
hardware triggers that are set by a previously connected debugger.
The 0.11 code already did this, but 0.13 did not.

To achieve this I decided to share the code to enumerate triggers
between 0.11 and 0.13, which required me to implement get_register() and
set_register() for 0.11, which made the whole change a lot larger than
you might have guessed.

Hopefully this sets us up to in the future share the code to set/remove
triggers as well.
2017-07-10 10:26:24 -07:00
Tim Newsome 6c627e9ea9 Add back support for type 1 triggers.
They were implemented, and people want to keep using them.
Also make OpenOCD tolerate cores that have $misa at 0xf10 instead of the
current address of 0x301.
Actually return an error when we fail to read a CSR.
Tweak cache_set32() debug output.
2017-07-03 11:01:10 -07:00
Tim Newsome b6f8efbf44 Check for errors in read_csr().
Also slightly improve debugging output.
2017-06-27 15:11:06 -07:00
Tim Newsome 64af052911 Fix the build.
Main change is to make riscv_addr_t be unsigned. The rest is mechanical
fixing of types, print statements, and a few signed/unsigned compares.

Smoketest indicates everything is working more or less as before.
2017-06-13 12:33:01 -07:00
Megan Wachs e12f5575ef riscv-v11: Don't perform unexpected operation in cache_write 2017-05-22 22:02:01 -07:00
Palmer Dabbelt 9d4df3420c Initialize all registers in examine
I'm not sure why this is necessary, but for some reason GDB is asking
for registers before OpenOCD thinks there's been a halt.  This is really
just a workaround, but I need to refactor the v0.11 stuff anyway so I
don't want to figure it out.
2017-04-26 15:09:24 -07:00
Palmer Dabbelt 8dea2908b7 Add 64-bit and multihart support
This is a major rewrite of the RISC-V v0.13 OpenOCD port.  This
shouldn't have any meaningful effect on the v0.11 support, but it does
add generic versions of many functions that will allow me to later
refactor the v0.11 support so it's easier to maintain both ports.  This
started as an emergency feature branch and went on for a long time, so
it's all been squashed down into one commit so there isn't a big set of
broken commits lying around.  The changes are:

 * You can pass "-rtos riscv" to the target in OpenOCD's configuration
   file, which enables multi-hart mode.  This uses OpenOCD's RTOS
   support to control all the harts from the debug module using commands
   like "info threads" in GDB.  This support is still expermental.

 * There is support for RV64I, but due to OpenOCD limitations we only
   support 32-bit physical addresses.  I hope to remedy this by rebasing
   onto the latest OpenOCD release, which I've heard should fix this.

 * This matches the latest draft version of the RISC-V debug spec, as of
   April 26th.  This version fixes a number of spec bugs and should be
   close to the final debug spec.
2017-04-26 09:10:49 -07:00
Tim Newsome 8af4a9a053 Update DMI bus width for 0.13.
Change-Id: Ieff13a7a0084fe822b7cc6d927727eba4f158ef0
2017-02-07 11:28:50 -08:00
Tim Newsome d055f86552 Most gdbserver tests pass now.
Change-Id: I14a8360d9cf2800ca5e6a44f7e58102b2baef719
2017-02-05 18:09:19 -08:00