Commit Graph

7995 Commits

Author SHA1 Message Date
Tim Newsome 753d15e22c Print out which port OpenOCD is listening on.
This is essential when a test environment asks OpenOCD to listen on port
0, so that the environment can easily discover which port is actually
being used.
2017-07-25 14:08:10 -07:00
Tomas Vanek 02bc718d1a flash Kinetis: fix probe for FlexNVM partitioned as EEPROM backup
If a MCU has FlexNVM partitioned as EEPROM backup only
(no data flash), kinetis_probe_chip() detects zero fcfg2_maxaddr1
and adjusts flash banks count to 1, what is obviously wrong.

The change limits the test to devices without FlexNVM.

Computation of program flash/FlexNVM blocks is now more robust.

Missing case 0x07 is added to switch (fcfg1_depart)

Change-Id: I0bd6030a0fe1ab62aeb0223bbdf2aee1505bf6a0
Reported-by: simon.haines@scalardata.com
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4180
Tested-by: jenkins
Reviewed-by: Simon Haines <simon.haines@scalardata.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-07-24 13:11:06 +01:00
Tomas Vanek dbd0d90af9 flash Kinetis: fix devices with smallest program flash (8 and 16 kB)
Change-Id: I2692b9877a7f877104528f279a69e8cc1cfbcdbf
Reported-by: David Miller Lowe <milhead@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4173
Tested-by: jenkins
Reviewed-by: Miller Lowe <miller.lowe@trailtech.net>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-07-24 13:09:37 +01:00
Tim Newsome 79329f21a3 Merge pull request #84 from riscv/reset
Fix infinite loop in reset.
2017-07-16 12:47:41 -07:00
Tim Newsome b032eb1bcc Use a wall clock timeout to complete reset. 2017-07-16 11:48:12 -07:00
Tim Newsome f0f1df1061 Fix infinite loop in reset. 2017-07-14 12:50:11 -07:00
Tim Newsome 43c6fd3b8f Merge pull request #83 from riscv/triggers
Share trigger code between 0.11 and 0.13 code.
2017-07-13 18:04:34 -07:00
Tim Newsome d60dbd60e8 Share trigger code between 0.11 and 0.13 code.
The actual implementation of triggers didn't change between those two
versions, so there's no need to duplicate the code.

In the process, I also fixed a minor multicore bug where tselect didn't
always get written on all harts.
2017-07-12 19:54:40 -07:00
Tim Newsome cc2c2e7a65 Merge pull request #82 from riscv/comment
Forgot to commit this follow up to PR #79
2017-07-12 19:45:40 -07:00
Tim Newsome 2deb02695e Forgot to commit this follow up to PR #79 2017-07-12 17:51:38 -07:00
Tim Newsome 46b91c9b0d Merge pull request #79 from riscv/abstract_regs
Use abstract command to access registers if possible
2017-07-12 17:50:46 -07:00
Tim Newsome 09bf86e31a Keep around cmderr for callers to inspect.
Use this to only change abstract register access behavior when cmderr
explicitly says the requested operation is unsupported.
2017-07-12 14:36:09 -07:00
Tim Newsome 856f70fe44 Try abstract register writes as well. 2017-07-12 14:13:31 -07:00
Tim Newsome f37e93bbc0 Try using abstract commands to read registers
This is the only way the spec guarantees that GPRs are accessible, and
depending on the implementation this might be the only way that CSRs are
accessible.

Also changed the debug code that parses out DMI fields to be simpler to
maintain (albeit a little slower).

riscv013_execute_debug_buffer() now automatically clears cmderr if the
command fails. That feels like the right behavior. (It does return the
error to its caller.)
2017-07-12 14:13:31 -07:00
Tim Newsome da74f511b9 Merge pull request #80 from riscv/triggers
Disable debugger-set triggers on connect
2017-07-11 12:13:56 -07:00
Palmer Dabbelt a0c1dd643a Merge pull request #81 from riscv/llp64
Use LL for 64-bit defines, as Windows is LLP64
2017-07-10 16:00:39 -07:00
Palmer Dabbelt 10a61000b5 Use LL for 64-bit defines, as Windows is LLP64
This should also fix bugs on ILP32 systems.
2017-07-10 13:45:42 -07:00
Tim Newsome 4072fa493b Disable debugger-set triggers on connect
When first connecting to a target, have the debugger disable any
hardware triggers that are set by a previously connected debugger.
The 0.11 code already did this, but 0.13 did not.

To achieve this I decided to share the code to enumerate triggers
between 0.11 and 0.13, which required me to implement get_register() and
set_register() for 0.11, which made the whole change a lot larger than
you might have guessed.

Hopefully this sets us up to in the future share the code to set/remove
triggers as well.
2017-07-10 10:26:24 -07:00
Andreas Fritiofson 29cfe9c5ee mips32: inline functions in headers must be static
Change-Id: If1d0fc6766cadc2db33408ae5c0968de6b7a1b94
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/4178
Tested-by: jenkins
Reviewed-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-by: Stian Skjelstad <stian@nixia.no>
2017-07-07 09:54:35 +01:00
Tim Newsome 29b62710f7 Merge pull request #78 from riscv/build32
Add 32-bit build
2017-07-06 15:03:12 -07:00
Tim Newsome 21e06e1d89 Fix 32-bit build.
Code taken from http://openocd.zylin.com/#/c/4178/
2017-07-06 14:53:28 -07:00
Tim Newsome 708b05ba07 Build 32- and 64-bit binaries with Travis. 2017-07-06 14:53:14 -07:00
Tim Newsome 31e5b53a46 Merge pull request #74 from riscv/build32
Fix 32-bit build errors.
2017-07-06 13:41:47 -07:00
Tim Newsome 9f1738ae49 Merge pull request #77 from riscv/travis
Perform regular build with travis.
2017-07-06 10:54:34 -07:00
Tim Newsome 3be99ac884 Perform regular build with travis. 2017-07-05 10:33:42 -07:00
Tim Newsome 321619946b Merge pull request #73 from riscv/old_triggers
Add back support for type 1 triggers
2017-07-03 13:52:16 -07:00
Palmer Dabbelt 3cff4213a4 Merge pull request #69 from riscv/multi-gdb
Fix the multi-GDB mode bugs
2017-07-03 13:18:06 -07:00
Palmer Dabbelt ce48a5d3da Merge pull request #72 from dmitryryzhov/examine_restore_temp_reg
Restore value of temporary register (s0) in examine OpenOCD procedure…
2017-07-03 12:43:47 -07:00
Tim Newsome 450307b66f Fix 32-bit build errors.
I only compiled the source. Didn't have the tooling installed to link.
Hopefully that's good enough.
Fixes #71.
2017-07-03 12:17:07 -07:00
Tim Newsome f18fd83ac7 Fix trigger set/clear bug. 2017-07-03 11:52:35 -07:00
Tim Newsome 6c627e9ea9 Add back support for type 1 triggers.
They were implemented, and people want to keep using them.
Also make OpenOCD tolerate cores that have $misa at 0xf10 instead of the
current address of 0x301.
Actually return an error when we fail to read a CSR.
Tweak cache_set32() debug output.
2017-07-03 11:01:10 -07:00
Dmitry Ryzhov 99a3673507 Fix comment about saving the temporary register in examine procedure. 2017-07-01 15:09:23 +03:00
Steven Stallion 0e4fbfba03 rtos: better sanity checking for uCOS-III
This patch improves the OSRunning check. If the rtos_running check
fails, update_threads will return an error rather than attempt to update
the thread list using bad values.

Change-Id: I8614c325504d3a9ab19aebb6862b1fe445a0c8e7
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/4166
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2017-06-30 21:23:47 +01:00
Steven Stallion e6fe4dddb9 rtos: style corrections for uCOS-III
This patch corrects a number of style infractions in RTOS support for
uC/OS-III. These were missed during initial review last year prior to
the 0.10.0 release.

Change-Id: Ia2139f6ca381d4087fd8ee989f7a03ac474d7440
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/4120
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2017-06-30 21:23:15 +01:00
Moritz Fischer 6767c1c1a3 zynq_7000: Add expected id for Zynq 7z100 devices
As found on the NI Project Sulfur SDR board.

Change-Id: I47bdd38ae85cf45cedad8797ea03bf3105153320
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-on: http://openocd.zylin.com/4176
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-06-30 21:21:27 +01:00
Dmitry Ryzhov 7d451e00f5 Restore value of temporary register (s0) in examine OpenOCD procedure in case of core can not execute 64 bit instruction. 2017-06-30 19:15:58 +03:00
Richard Watts b3cf9a665c flash/nor/efm32: Support EZR32HG devices.
Recognise the family number for Silicon Labs EZR32HG devices and
select the correct flash page size.

Change-Id: I876e930f3a9f679557fa0d0acac33e9bbfb28c46
Signed-off-by: Richard Watts <rrw@kynesim.co.uk>
Reviewed-on: http://openocd.zylin.com/3934
Tested-by: jenkins
Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com>
Reviewed-by: Jonas Norling <jonas.norling@cyanconnode.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-06-30 10:57:20 +01:00
Andreas Fritiofson 868a100143 target: Fix snprintf format string and argument mismatch in md output
Commit 47b8cf842 changed the fixed type of the value argument to snprint
but didn't change the format string to match for sizes != 64 bit.

Change-Id: I908b06f49ab69d04224282949190a0de883048e0
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/4167
Tested-by: jenkins
Reviewed-by: Stian Skjelstad <stian@nixia.no>
Reviewed-by: Philipp Guehring <pg@futureware.at>
2017-06-30 10:06:32 +01:00
Tim Newsome b6f8efbf44 Check for errors in read_csr().
Also slightly improve debugging output.
2017-06-27 15:11:06 -07:00
Palmer Dabbelt d77c4a953c Don't set breakpoints on disabled harts 2017-06-21 12:25:20 -07:00
Palmer Dabbelt 689d0fcaf6 No longer hard-code the non-RTOS hart to 0
I was just being lazy here.
2017-06-21 12:25:19 -07:00
Palmer Dabbelt 4bdb042224 Allow memory writes to proceed on all harts 2017-06-21 12:25:19 -07:00
Palmer Dabbelt a277416a39 Refactor examine, to avoid some assertions
Now that we're supporting non-RTOS multi-hart mode there's some more
assertions that you're running on the right hart.  Those assertions
aren't sane very early in examine, so I avoid them.
2017-06-21 12:25:19 -07:00
Palmer Dabbelt 788908fcf0 Factor out checking if harts should be used
Rather than having a bunch of "if rtos" stuff, I now just check "if
hart_enabled".  This makes some code paths cleaner, all of which were
buggy in the non-RTOS multi-hart mode.
2017-06-21 10:09:16 -07:00
Palmer Dabbelt 9f4cac5a38 Set current_hartid from coreid
This avoids a bunch of RTOS special cases.
2017-06-20 17:19:05 -07:00
Palmer Dabbelt 4e2e730abe Merge pull request #68 from riscv/multicore
Testsuite now passes on multicore target
2017-06-20 14:20:00 -07:00
Tim Newsome 9cd98058a0 Set hardware triggers on all harts.
Right now we're using "threads" to represent harts. gdb/OpenOCD assume
there's only one set of hardware breakpoints among all threads. Make it
so.
2017-06-20 13:10:35 -07:00
Tim Newsome 10518351bb Don't immediately segfault with -rtos on v0.11. 2017-06-20 11:32:42 -07:00
Tim Newsome ccdd26e3ef Comment curious code. 2017-06-20 11:32:42 -07:00
Tim Newsome 927f9d8873 Update list of "threads" when harts are discovered.
This ensures that "info threads" is accurate as soon as gdb connects.
Also print out number of triggers that is discovered in examine().
2017-06-20 11:32:42 -07:00