ARM documentation for Cortex-M reports the field 'implementer' in
the register CPUID.
OpenOCD used the miss-spelled 'implementor'. Fix it!
Change-Id: I854d223971ae7a49346e1f7491c2c0415f5e2c1d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8318
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Add Cortex-M52 to the list of known Cortex-M implementations to
allow detection of the core.
Values checked against the ARM document "Arm China Cortex®-M52
Processor Technical Reference Manual" 102776_0002_06_en.
Reported-by: Joseph Yiu <Joseph.Yiu@arm.com>
Change-Id: Id0bde8a0476f76799b7274835db9690f975e2dd6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8317
Tested-by: jenkins
The detection of Cortex-M STAR-MC1 was introduced with [1], at a
time when OpenOCD was only checking the field PartNo of the CPUID
register.
Later-on [2], OpenOCD extended the check to the field implementer
of CPUID register. The value for ARM (0x41) implementer was used
to all the Cortex-M, but no feedback for STAR-MC1 was available. A
comment reporting the possible mismatch was added.
As reported on OpenOCD mailing-list, the technical reference manual
for STAR-MC1 is now available [3] and it reports the implementer
as ARM China (0x63) [3].
Fix the STAR-MC1 implementer accordingly.
Reported-by: Joseph Yiu <Joseph.Yiu@arm.com>
Change-Id: I8ed1064a847b73065528ee7032be967b5c58b431
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Link: [1] 7dc4be3157 ("target/arm: Add support with identify STAR-MC1")
Fixes: [2] 05ee889155 ("target/cortex_m: check core implementor field")
Link: [3] https://www.armchina.com/download/Documents/Application-Notes/Technical-Reference-Manual?infoId=160
Reviewed-on: https://review.openocd.org/c/openocd/+/8316
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Add space around math operators.
Change-Id: I50fce3da283a78ba02bf70b6a752f7bf778d79f5
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7585
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
When an asynchronous exception occurs at the same time
as a breakpoint event (either hardware breakpoint or software breakpoint),
it is possible for the processor to halt at the beginning of the
exception handler instead of the instruction address pointed
by the breakpoint.
During debug entry in exception handler state and with BKPT bit set
as the only break reason in DFSR, check if there is a breakpoint, which
have triggered the debug halt. If there is no such breakpoint,
resume execution. The processor services the interrupt and
halts again at the correct breakpoint address.
The workaround is not needed during target algo run (debug_execution)
because interrupts are disabled in PRIMASK register.
Also after single step the workaround resume never takes place:
the situation is treated as error.
Link: https://developer.arm.com/documentation/SDEN1068427/latest/
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I8b23f39cedd7dccabe7e7066d616fb972b69f769
Reviewed-on: https://review.openocd.org/c/openocd/+/8332
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Liviu Ionescu
Most of the work is already done by [1].
Remove few more '_s' suffix and also fix some comment referring to
the old name of the struct.
Link: https://review.openocd.org/c/openocd/+/8340
Change-Id: Ifddc401c3b05e62ece3aa7926af1e78f0c4a671e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8341
Reviewed-by: zapb <dev@zapb.de>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Commit f9509c92db ("itm: rework itm commands before 'init'")
ignores the default enable of ITM channel 0, that is applied when
no 'itm port[s]' is issued.
Call armv7m_trace_itm_config() unconditionally to handle it.
Change-Id: I3e85d0b063ed38c1552f6af9ea9eea2e76aa9025
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Paul Fertser <fercerpav@gmail.com>
Fixes: f9509c92db ("itm: rework itm commands before 'init'")
Reviewed-on: https://review.openocd.org/c/openocd/+/7900
Reviewed-by: <post@frankplowman.com>
Tested-by: jenkins
The register SPSR_EL1 is accessible and it's content is relevant
only when the target is in EL1 or EL2 or EL3.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd5384000, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $SPSR_EL1
or through OpenOCD command
reg SPSR_EL1
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Change-Id: Ia0f984d52920cc32b8ee31157d62c13dea616a3a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8276
Tested-by: jenkins
The register ESR_EL1 is accessible and it's content is relevant
only when the target is in EL1 or EL2 or EL3.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd5385200, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ESR_EL1
or through OpenOCD command
reg ESR_EL1
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Change-Id: Icd65470c279e5cfd03091db6435cdaa1c447644c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8275
Tested-by: jenkins
The register ELR_EL1 is accessible and it's content is relevant
only when the target is in EL1 or EL2 or EL3.
Without this patch, an error:
Error: Opcode 0xd5384020, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ELR_EL1
or through OpenOCD command
reg ELR_EL1
Detect the EL and return error if the register cannot be accessed.
Change-Id: I402dda4cd9dae502b05572fc6c1a8f0edf349bb1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8274
Tested-by: jenkins
The register SPSR_EL2 is accessible and it's content is relevant
only when the target is in EL2 or EL3.
Virtualization SW in EL1 can also access it, but this either
triggers a trap to EL2 or returns SPSR_EL1. Debugger should not
mix the real SPSR_EL2 with the virtual register.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd53c4000, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $SPSR_EL2
or through OpenOCD command
reg SPSR_EL2
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Change-Id: If3792296b36282c08d597dd46cfe044d6b8288ea
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8273
Tested-by: jenkins
The register ESR_EL2 is accessible and it's content is relevant
only when the target is in EL2 or EL3.
Virtualization SW in EL1 can also access it, but this either
triggers a trap to EL2 or returns ESR_EL1. Debugger should not mix
the real ESR_EL2 with the virtual register.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd53c5200, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ESR_EL2
or through OpenOCD command
reg ESR_EL2
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Change-Id: Icb32b44886d50907f29b068ce61e4be8bed10208
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8272
Tested-by: jenkins
The register ELR_EL2 is accessible and it's content is relevant
only when the target is in EL2 or EL3.
Virtualization SW in EL1 can also access it, but this either
triggers a trap to EL2 or returns ELR_EL1. Debugger should not mix
the real ELR_EL2 with the virtual register.
Without this patch, an error:
Error: Opcode 0xd53c4020, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ELR_EL2
or through OpenOCD command
reg ELR_EL2
Detect the EL and return error if the register cannot be accessed.
Change-Id: Idf02b42a7339df83260c1e44ceabbb05fbf392b9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8271
Tested-by: jenkins
The register SPSR_EL3 is accessible and it's content is relevant
only when the target is in EL3.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd53e4000, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $SPSR_EL3
or through OpenOCD command
reg SPSR_EL3
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Change-Id: I00849d99feeb96589c426fcafda98127dbd19a67
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8270
Tested-by: jenkins
The register ESR_EL3 is accessible and it's content is relevant
only when the target is in EL3.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd53e5200, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ESR_EL3
or through OpenOCD command
reg ESR_EL3
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Drop the FIXME comment on Aarch32 case, as the register exists in
Aarch64 only.
Change-Id: Ie8c69dc7b50ae81a52506cf151c8e64e15752d0d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8269
Tested-by: jenkins
The register ELR_EL3 is accessible and it's content is relevant
only when the target is in EL3.
Without this patch, an error:
Error: Opcode 0xd53e4020, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ELR_EL3
or through OpenOCD command
reg ELR_EL3
Detect the EL and return error if the register cannot be accessed.
Change-Id: I545abb196e5c34e462c7e5d5d3ec952e588642da
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8268
Tested-by: jenkins
The command 'gdb_report_register_access_error' is used to silence
errors while reading registers and not reporting them to GDB.
Nevertheless, the error is printed by a LOG_ERROR() in armv8_dpm.
Change the message to LOG_DEBUG().
It will still cause the error to be propagated and eventually
printed by the caller (e.g. by the command 'reg').
Change-Id: Ic0db74fa28235d686ddd21a5960c52ae003e0931
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8267
Tested-by: jenkins
These functions are today always called with non-NULL parameter
regval, so the actual check is not needed.
Anyway, for any future code change, check the parameter at the
entry of the functions and return error if it is not valid.
Simplify the check to assign the result value and align the code
of the two functions.
Change-Id: Ie4d98063006d70d9e2bcfc00bc930133caf33515
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8266
Tested-by: jenkins
Use LOG_TARGET_ERROR() to print the error messages and additionally add
a reference to the related target.
Change-Id: I06722f3911ef4034fdd05dc9b0e2571b01b657a4
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8314
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
cortex_m_poll_one() detects reset testing S_RESET_ST sticky bit.
If the signal comes unexpectedly, poll must return TARGET_RESET state.
On the contrary in case of polling inside of an OpenOCD reset command,
TARGET_RESET has been has already been set and we need to get out of
it as quickly as possible.
The original code needs 2 polls: the first clears S_RESET_ST
and keeps TARGET_RESET state, the current TARGET_RUNNING or TARGET_HALTED
is reflected as late as the second poll is done.
Change the logic to keep in TARGET_RESET only when necessary.
See also [1]
Link: [1] 8284: tcl/target: ti_cc3220sf: Use halt for CC3320SF targets | https://review.openocd.org/c/openocd/+/8284
Fixes: https://sourceforge.net/p/openocd/tickets/360/
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I759461e5f89ca48a6e16e4b4101570260421dba1
Reviewed-on: https://review.openocd.org/c/openocd/+/8285
Tested-by: jenkins
Reviewed-by: Dhruva Gole <d-gole@ti.com>
In case of fail to allocate 'obj->name', the memory allocated for
'obj->out_filename' is not freed, thus leaking.
Since 'obj' is allocated with calloc(), thus zeroed, switch to use
the common error exit path for both allocations of 'obj->name' and
'obj->out_filename'.
Fixes: 2506ccb509 ("target/arm_tpiu_swo: Fix division by zero")
Change-Id: I412f66ddd7bf7d260cee495324058482b26ff0c5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8300
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
this functionality allows to query if a target belongs to some smp group
and to dynamically turn on/off smp-specific behavior
Change-Id: I67bafb1817c621a38ae4a2f55e12e4143e992c4e
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8296
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
For some target, the API assert_reset() checks if the target has
been examined, with target_was_examined(), to perform conditional
operations like:
- assert adapter's srst;
- write some register to catch the reset vector;
- invalidate the register cache.
Targets created with -defer-examine gets the examine flag reset
right before entering in their assert_reset(), disrupting the
actions above.
For targets created with -defer-examine, move the reset examine
after the assert_reset().
Change-Id: If96e7876dcace8905165115292deb93a3e45cb36
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8293
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Few files include target_type.h even if it is not needed.
Drop the include.
Other files access directly to target type's name instead of using
the proper API target_type_name().
Use the API and drop the include.
Change-Id: I86c0e0bbad51db93500c0efa27b7d6f1a67a02c2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8260
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Do not free the service in 'connection_closed_handler' because it is
free'd by the server infrastructure.
Checkpatch-ignore: COMMIT_LOG_LONG_LINE
This error was detected with valgrind:
==272468== Invalid free() / delete / delete[] / realloc()
==272468== at 0x484B27F: free (in /usr/libexec/valgrind/vgpreload_memcheck-amd64-linux.so)
==272468== by 0x1F34C7: remove_service (server.c:374)
==272468== by 0x2ED3D5: semihosting_tcp_close_cnx (semihosting_common.c:1819)
==272468== by 0x2ED3D5: handle_common_semihosting_redirect_command (semihosting_common.c:1926)
==272468== by 0x1FC703: exec_command (command.c:520)
==272468== by 0x1FC703: jim_command_dispatch (command.c:931)
==272468== by 0x36980F: JimInvokeCommand (in /home/marc/openocd/build/src/openocd)
==272468== by 0x1FFFFFFFFF: ???
==272468== by 0x53ED09F: ???
==272468== by 0x300000001: ???
==272468== by 0x1FFEFFF7FF: ???
==272468== by 0x3D3984: ??? (in /home/marc/openocd/build/src/openocd)
==272468== by 0x2: ???
==272468== Address 0x5fff650 is 0 bytes inside a block of size 24 free'd
==272468== at 0x484B27F: free (in /usr/libexec/valgrind/vgpreload_memcheck-amd64-linux.so)
==272468== by 0x2ECA42: semihosting_service_connection_closed_handler (semihosting_common.c:1807)
==272468== by 0x1F2E39: remove_connection.isra.0 (server.c:164)
==272468== by 0x1F349E: remove_connections (server.c:350)
==272468== by 0x1F349E: remove_service (server.c:364)
==272468== by 0x2ED3D5: semihosting_tcp_close_cnx (semihosting_common.c:1819)
==272468== by 0x2ED3D5: handle_common_semihosting_redirect_command (semihosting_common.c:1926)
==272468== by 0x1FC703: exec_command (command.c:520)
==272468== by 0x1FC703: jim_command_dispatch (command.c:931)
==272468== by 0x36980F: JimInvokeCommand (in /home/marc/openocd/build/src/openocd)
==272468== by 0x1FFFFFFFFF: ???
==272468== by 0x53ED09F: ???
==272468== by 0x300000001: ???
==272468== by 0x1FFEFFF7FF: ???
==272468== by 0x3D3984: ??? (in /home/marc/openocd/build/src/openocd)
==272468== Block was alloc'd at
==272468== at 0x484DA83: calloc (in /usr/libexec/valgrind/vgpreload_memcheck-amd64-linux.so)
==272468== by 0x2ED326: handle_common_semihosting_redirect_command (semihosting_common.c:1931)
==272468== by 0x1FC703: exec_command (command.c:520)
==272468== by 0x1FC703: jim_command_dispatch (command.c:931)
==272468== by 0x36980F: JimInvokeCommand (in /home/marc/openocd/build/src/openocd)
==272468== by 0x1FFFFFFFFF: ???
==272468== by 0x53ED09F: ???
==272468== by 0x400000002: ???
==272468== by 0x1FFEFFF7FF: ???
==272468== by 0x3D3984: ??? (in /home/marc/openocd/build/src/openocd)
==272468== by 0x2: ???
==272468==
Change-Id: I3e5323f145a98d1ff9ea7d03f87ed96140f49a18
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8257
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Currently, errors in pre/post-enable events are ignored and capturing is
always started, even if necessary device configuration fails. This
behaviour is confusing to users. Also, the TPIU must be disabled before
re-configuration is possible.
Start capturing and enable TPIU only if no errors in pre/post-enable
events occurred.
Change-Id: I422033e36ca006e38aa4504d491b7947def1237a
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8254
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
When external capturing is configured (default), the SWO pin frequency
is required. Enforce this to avoid a division by zero error.
While at it, ensure that the 'out_filename' variable always contains a
valid string. This saves a few checks and makes the code more clean and
readable.
Change-Id: If8c1dae9549dd10e2f21d5b896414d47edac9fc2
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8224
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
For MPU configs, determine memory access rights
by probing protection TLB. Issuing IHI without execute
permissions can trigger an exception.
No new clang static analyzer warnings.
Change-Id: Iea8eab5c2113df3f954285c3b9a79e96d41aa941
Signed-off-by: Ian Thompson <ianst@cadence.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8080
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Historically, the function cortex_a_dap_write_memap_register_u32()
was used to discriminate the register write in APB-AP CPU debug
against the complex memory access in AHB-AP memory bus.
It has no sense to keep the function and its comment.
Plus, by forcing atomic write it impacts the debug performance.
Drop it!
A further rework to enqueue sequence of atomic writes is needed.
Change-Id: I2f5e9015f0e27fa5a6d8337a1ae25e753e2e1d26
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8231
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Tested-by: jenkins
The command 'cache auto' was introduced with commit cd440bd32a
("add armv7a_cache handlers") in 2015 to allow disabling the cache
handling done automatically by OpenOCD.
This was probably a way to test the cache handling when there were
still the two independent accesses for APB-AP CPU debug and for
AHB-AP memory bus.
The handling of cache for cortex_a is robust and there is no more
reason to disable it.
The command 'cache auto' is not used in any upstream script.
On target aarch64 this command has never been introduced as the
cache is always handled automatically by OpenOCD.
Drop the command 'cache auto' and add it in the deprecated list.
Drop the flag 'auto_cache_enabled' by considering it as true.
Rename the function 'armv7a_cache_auto_flush_all_data()' as
'armv7a_cache_flush_all_data()' and, while there, fix the error
propagation in SMP case.
Change-Id: I0399f1081b08c4929e0795b76f4a686630f41d56
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8230
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
The initial OpenOCD code for Cortex-A (ARMv7a) [1] was merged in
2009 but, due to lack of public documentation for ARMv7a, it was
almost a simple copy/paste from the existing code for Cortex-M
(ARMv7m).
On Cortex-M the same AP provides access to both CPU debug and CPU
memory. This feature is not present on ARMv7a.
To still keep some communality with ARMv7m code, the change [2]
splits the CPU debug access from the CPU memory access by using
two independent AP; this is copied from the system architecture of
TI OMAP3530 which provides to DAP a direct AHB-AP memory bus on
AP#0, separated from AP#1 for the APB-AP CPU debug.
But the direct memory access through the system bus breaks the
coherency between memory and CPU caches, so change [3] added some
cache invalidation to avoid issues.
The code to allow ARMv7a CPU to really read/write in CPU memory
was added by change [4] in 2011. Such still not optimized
implementation was very slow, so it did not replace the access
through the system bus. A selection through DAP's 'apsel" command
was used to select between the two modes.
Only in 2015, with change [5], the speed of CPU read/write was
improved using the DCC_FAST_MODE. But the direct access to the
memory through the system bus remained.
Finally, with change [6] in 2018 the system bus access was dropped
for good, as the new virtual target "mem_ap" could implement such
access in a more clean way.
Only memory access through CPU remained for ARMv7a.
Nevertheless, a useless cache invalidation remained in the code,
decreasing the speed of the write access.
Drop the useless cache invalidate on CPU memory write and the
associated comment, not anymore valid.
Drop the now unused function armv7a_cache_auto_flush_on_write().
This provides a speedup of between 4 and 8, depending on adapter
and JTAG/SWD speed.
Link: [1] 7a93100c2d ("Add minimalist Cortex A8 file")
Link: [2] 1d0b276c9f ("The rest of the Cortex-A8 support from Magnus: ...")
Link: [3] d4e4d65d28 ("Cache invalidation when writing to memory")
Link: [4] 05ab8bdb81 ("cortex_a9: implement read/write memory through APB-AP")
Link: [5] 0228f8e827 ("Cortex A: fix extra memory read and non-word sizes")
Link: [6] fac9be64d9 ("target/cortex_a: remove buggy memory AP accesses")
Change-Id: Ifa3c7ddf2698b2c87037fb48f783844034a7140e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8229
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
The gdb subsystem is initialized after the first target examine,
so the field struct target::gdb_service is NULL during examine.
A command "smp off" in the examine event handler causes a SIGSEGV
during OpenOCD startup.
Check for pointer not NULL before dereferencing it.
Change-Id: Id115e28be23a957fef1b97ab66d7273f0ea0dce4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8216
Tested-by: jenkins
The code for cortex_a allocates the register cache during the very
first examine of the target.
To prevent a segmentation fault in assert_reset(), the call to
register_cache_invalidate() is guarded by target_was_examined().
But for targets with -defer-examine, the target is set as not
examined in handle_target_reset() just before entering in
assert_reset().
This causes registers to not be invalidated while reset a target
examined but with -defer-examine.
Change the condition and invalidate the register cache if it has
been already allocated.
Change-Id: I81ae782ddce07431d5f2c1bea3e2f19dfcd6d1ce
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8215
Tested-by: jenkins
The code for aarch64 allocates the register cache during the very
first examine of the target.
To prevent a segmentation fault in assert_reset(), the call to
register_cache_invalidate() is guarded by target_was_examined().
But for targets with -defer-examine, the target is set as not
examined in handle_target_reset() just before entering in
assert_reset().
This causes registers to not be invalidated while reset a target
examined but with -defer-examine.
Change the condition and invalidate the register cache if it has
been already allocated.
Change-Id: Ie13abb0ae2cc28fc3295d678c4ad1691024eb7b8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8214
Tested-by: jenkins
Prevent a segmentation fault by preventing to try to halt a target
that has not been examined yet.
Change-Id: I5d344e7fbdb5422f7c5e2c39bdd48cbc6c2a3e58
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8213
Tested-by: jenkins
Commit 16b4b8cf54 ("Cortex-M3: expose most DWT registers") added
the DWT registers to the list of CPU registers.
The commit message from 2009 reports the reason behind this odd
mixing of CPU and DWT registers.
This feature got broken in 2017 with the introduction of the field
struct reg::exist and its further use in the code. As result, the
command 'reg' on a target Cortex-M reports only the core registers
and then the header line
===== Cortex-M DWT registers
not anymore followed by the DWT registers.
Fix it by tagging each DWT registers as existing.
Change-Id: Iab026e7da8d6b8ba052514c3fd3b5cdfe301f330
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: b5964191f0 ("register: support non-existent registers")
Reviewed-on: https://review.openocd.org/c/openocd/+/8198
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Initialized `value` variables that could only be set in a branch.
Change-Id: Iec7413ade9d053c93352a58ff954ad49a6545923
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8179
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Move setting of do_reconnect flag from swd_run_inner()
to swd_run(). Reconnect is not used at the inner level
and the flag had to be cleared after swd_run_inner()
to prevent recursion.
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: Ib1de80bbdf10d1cbfb1dd351c6a5658e50d12af2
Reviewed-on: https://review.openocd.org/c/openocd/+/8155
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
The file 'list.h', copied from FreeBSD, does not depend from any
OpenOCD specific include file, but only needs 'stddef.h' for the
type 'size_t'.
Let 'list.h' to include the correct header file, then fix the now
broken dependencies in the other files that were incorrectly
relying on 'list.h' to include 'helper/types.h'
Change-Id: Idd31b5bf607e226cac44ef41b2aa335ae4dbf519
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8173
Tested-by: jenkins
Add access to fpr and cp1 registers.
GDB can now check the FPRs with `info reg f` and change them.
Checkpatch-ignore: MACRO_ARG_REUSE
Change-Id: I63896ab6f6737054d8108db105a13a58e1446fbc
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7866
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Extend the existing code to support Monitor mode in AArch32.
Change-Id: Ia43df98d1497baac48aea67b92d81344c24f0635
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8169
Tested-by: jenkins
ADIv6 brought more complicated rules for DP reg 0 banking.
Neither the original implementation [1] nor the later
modification [2] respected that the DP reg 0 is banked
for read only, not for write. Enforcing of an useless
SELECT write before a write to ABORT register may trigger
FAULT (CTRL/STAT bits ORUNDETECT and STICKYORUN are set)
or WAIT (DP is stalled by an outstanding previous operation)
and therefore make ABORT register virtually unusable
on some adapters (bitbang, CMSIS-DAP).
There are DP ABORT specific functions swd_queue_ap_abort()
and swd_clear_sticky_errors() which worked around the problem
using the lowest level swd->write_reg(). Using a specific
write procedure for a single DP register was error prone
(there are other DP_ABORT writes using swd_queue_dp_write_inner())
and also the Tcl command 'xx.dap dpreg 0 value' suffered
from unwanted SELECT write.
Other smaller discords in DP banking probably do not
influence normal DP operation however they may complicate
debugging in corner cases.
Adhere strictly to the DP banking rules for both ADI versions.
Fixes: [1] commit 72fb88613f ("adiv6: add low level swd transport")
Fixes: [2] commit ee3fb5a0ea ("target/arm_adi_v5: fix DP SELECT logic")
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I3328748c1c3e0661c5ecd6eb070ac519b190ace2
Reviewed-on: https://review.openocd.org/c/openocd/+/8154
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Allow direct pointer to struct adiv5_private_config
for targets with adiv5_private_config inside of a bigger
private config container. Use it instead of the private_config
pointer toggling hack in aarch64.c
Allow optional use of -dap parameter and use it instead
of the static variable hack in xtensa_chip.c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I7260c79332940adfa49d57b45cae39325cdaf432
Reviewed-on: https://review.openocd.org/c/openocd/+/8138
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add access to dsp registers and a command for dsp related operations.
Checkpatch-ignore: MACRO_ARG_REUSE
Change-Id: I30aec0b9e4984896965edb1663f74216ad41101e
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7867
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
After commit d9b2607ca0 ("gdb_server: support sparse register
maps"), GDB crashes while requesting the value of 'cpsr' because
the fake register is tagged as not existing.
Change the logic and set all register as existing, while still
limiting the list for the initial GDB request at connect.
Change-Id: I1c4e274c06147683db2a59a8920ae5ccd863e15c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8163
Tested-by: jenkins
For the sake of https://review.openocd.org/c/openocd/+/7957
Instead of "coreid", 'target smp' command call order used as
an index
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Iab86b81868d37c0bf8663707ee11367c41f6b96d
Reviewed-on: https://review.openocd.org/c/openocd/+/8162
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Ian Thompson
Antonio Borneo
Mark Zhuang
Tomas Vanek
Marc Schink
Evgeniy Naydanov
Parshintsev Anatoly
Walter Ji
Erhan Kurubas