This adds support for the LS1046A Reference Design Board. There are
several JTAG headers accessable once the case is opened, but this config
is for the externally-accessable CMSIS DAP.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I0f83470da3758f0c4512ce47348c4db7de17b27e
Reviewed-on: https://review.openocd.org/c/openocd/+/6855
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The LS1046A is a quad-core processor from NXP in the layerscape family.
This SoC is a bit tricky to program: while the AArch64 CPUs are
little-endian, most of the peripherals are big-endian. Care must be
taken when interpreting memory reads/writes. This processor is in the
same family as the ls1012a, so the setup is similar.
If you use OpenOCD to attach early in the boot process, only the cpu0
may be available. Trying to halt other CPUs will fail. To avoid this,
defer examination of cpus 1-3, and provide a core_up helper (like e.g.
zynqmp).
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: If5a1a9441fb35fea3e05dc708b42e0cb3bbf2a54
Reviewed-on: https://review.openocd.org/c/openocd/+/6854
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Original TLC syntax uses 'set varname' to retrieve the value of
variable 'varname'. Such archaic syntax is still valid, but the
shorter '$varname' makes the code easier to read.
Replace 'set varname' with '$varname'.
While there, remove some useless curly brackets.
Change-Id: I27310e8c05afe56ea8bd0e41d4ae2c34447b725c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6863
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Add support for the latest in TI k3 family AM625 SoC.
For further details, see https://www.ti.com/lit/pdf/spruiv7
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: Ia54d0eab1c30a973afb1c2c61f4c5a72d29d9b78
Reviewed-on: https://review.openocd.org/c/openocd/+/6798
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add support for the latest in TI k3 family J721S2 SoC.
For further details, see http://www.ti.com/lit/pdf/spruj28
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I608ab4513ffb6b5c4166ba423e7d0dddbbb3bbfd
Reviewed-on: https://review.openocd.org/c/openocd/+/6796
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Since we can detect the type of target as well, reuse the _cpu_no_smp_up
function name and use the target name to simplify the _up function and
maintain consistency with what we introduced for r5.
Lets introduce gdb-attach event in a much cleaner fashion.
NOTE: we add a halt 1000 to retain the default gdb-attach hook behavior
While at it, fix a minor type of s/are/as in "Set Default target are
core 0" and simplify the foreach usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I3259b7c3ae4c71b06d921edfaefe17c03bb673dc
Reviewed-on: https://review.openocd.org/c/openocd/+/6616
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Since we can detect the type of target as well, make the attach
function name generic for the follow on cleanup patch on armv8 to use
as well.
Lets introduce gdb-attach event in a much cleaner fashion. We can
introduce a simpler r5_up function since we now have more descriptive
core names making the individual descriptive procs redundant.
NOTE: we add a halt 1000 to retain the default gdb-attach hook behavior
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I31506bb2b86e63638082640eb72aa7c4c9575e93
Reviewed-on: https://review.openocd.org/c/openocd/+/6617
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
R5 targets are currently named r5.0..n and the only way for user to
determine the actual type is external documentation. Lets just rename
the target names to make them descriptive to not require external
documentation for finding which R5 to connect to.
NOTE: we leave the _mcu_r5_cores _main0_r5_cores _main1_r5_cores alone
for now to allow existing startup proc functions to work, but we will
drop it in the follow on patch.
Previously:
Info : starting gdb server for j721e.cpu.r5.0 on 3336
Info : Listening on port 3336 for gdb connections
Info : starting gdb server for j721e.cpu.r5.1 on 3337
Info : Listening on port 3337 for gdb connections
Info : starting gdb server for j721e.cpu.r5.2 on 3338
Info : Listening on port 3338 for gdb connections
Info : starting gdb server for j721e.cpu.r5.3 on 3339
Info : Listening on port 3339 for gdb connections
Info : starting gdb server for j721e.cpu.r5.4 on 3340
Info : Listening on port 3340 for gdb connections
Info : starting gdb server for j721e.cpu.r5.5 on 3341
Info : Listening on port 3341 for gdb connections
With this patch:
Info : starting gdb server for j721e.cpu.mcu_r5.0 on 3336
Info : Listening on port 3336 for gdb connections
Info : starting gdb server for j721e.cpu.mcu_r5.1 on 3337
Info : Listening on port 3337 for gdb connections
Info : starting gdb server for j721e.cpu.main0_r5.0 on 3338
Info : Listening on port 3338 for gdb connections
Info : starting gdb server for j721e.cpu.main0_r5.1 on 3339
Info : Listening on port 3339 for gdb connections
Info : starting gdb server for j721e.cpu.main1_r5.0 on 3340
Info : Listening on port 3340 for gdb connections
Info : starting gdb server for j721e.cpu.main1_r5.1 on 3341
Info : Listening on port 3341 for gdb connections
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I2989efe3ae3e16754f98fa1dc9363ec4c898f7c3
Reviewed-on: https://review.openocd.org/c/openocd/+/6627
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The MCU is present on few of the SoCs and is meant as General Purpose
(GP) MCU of the system. Lets rename it to make clear what we are
debugging - esp when multiple MCUs are present in the system.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I16132d321daf6e9b1d893fe6f92026d5aa9eb152
Reviewed-on: https://review.openocd.org/c/openocd/+/6619
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The M3 is the system controller of the system. Lets rename it to make
clear what we are debugging - esp when multiple MCUs are present in the
system.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I4cd03b6068b8ce140fd254f9dd88151c4c7006d7
Reviewed-on: https://review.openocd.org/c/openocd/+/6618
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add gdb-attach event to call the "up" function of m3 and m4 allowing for
more seamless integration with gdb for end users. We still retain _up
functions for non-gdb functionality.
NOTE: we add a halt 1000 to retain the default gdb-attach hook behavior
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I2e51fdbd8756f156551e589c748c3a338afa655c
Reviewed-on: https://review.openocd.org/c/openocd/+/6615
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
both stm32l5x and stm32u5x configs are almost identical except
clock config.
while at there rename target procs to avoid issues with JTAG daisy
chaining.
Change-Id: Ibbb1dfeb91a7f8d5d45744cf57dca2877f60e0c5
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6596
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
This adds a board file for the NXP LS1088ARDB. This only covers the
"primary" JTAG header J55, and not the PCIe header (J91). The only
oddity is that the LS1088A and CPLD are muxed by adding/removing a
jumper from J48. Unfortunately, it doesn't look like OpenOCD supports
this CPLD beyond determining the irlen, so it's not very useful. Those
who are interested in experimenting can define CWTAP to access the CPLD,
but the default is to access the CPU.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: Ia07436a534f86bd907aa5fe2a78a326a27855a24
Reviewed-on: https://review.openocd.org/c/openocd/+/6849
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Normally the service processor is not necessary for debugging. However,
if you are using the hard-coded RCW or your boot source is otherwise
corrupt, then the general purpose processors will never be released from
hold-off. This will cause GDB to become confused if it tries to attach,
since they will appear to be running arm32 processors. To deal with
this, we can release the CPUs manually with the BRRL register. This
register cannot be written to from the axi target, so we need to do it
from the service processor target. This involves halting the service
processor, modifying the register, and then resuming it again. We try
and determine what state the service processor was in to avoid resuming
it if it was already halted.
The reset vector for the general purpose processors is determined by the
boot logation pointer registers in the device configuration unit.
Normally these are set using pre-boot initialization commands, but if
they are not set then they default to 0. This will cause the CPU to
almost immediately hit an illegal instruction. This is fine because we
will almost certainly want to attach to the processor and load a program
anyway.
I considered adding this as an event handler for either gdb-attach or
reset-init. However, this command shouldn't be necessary most of the
time, and so I don't think we should run it automatically.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I1b725292d8a11274d03af5313dc83678e10e944c
Reviewed-on: https://review.openocd.org/c/openocd/+/6850
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The LS1088A is an octo-core aarch64 processor from NXP in the layerscape
family. The JTAG is undocumented, but I was able to figure things out
from the output of `dap info`. This is the first in-tree example of
using the hwthread rtos (as far as I know), so hopefully it can serve as
an example to other developers. There are some ETMs, but I was unable to
try them out because I got 'invalid command name "etm"' when trying to
test things out.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I9b0791d27d8c41170a413a8d86431107a85feba2
Reviewed-on: https://review.openocd.org/c/openocd/+/6848
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
According to the datasheet, the minimum clock period with Vccio1 = 1.5V
(the lowest voltage supported) is 143ns, or around 6MHz. Set the default
adapter speed to 5 MHz.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I21cad33fa7f1e25e81f43b5d2214d1fa4ec924de
Reviewed-on: https://review.openocd.org/c/openocd/+/6847
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This adds some additional IDCODEs from the datasheet. It also adds
support for customizing the tap name.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I7cda10b92c229b61836c12cd9ca410de358ede2e
Reviewed-on: https://review.openocd.org/c/openocd/+/6846
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Changed flash driver to support writing to the user data page, as well as to any portion of the lockbits page above 512 bytes (the amount used for the actual page lock words). The top part of the lockbits page is used on at least the EFR32xG1 chips for the SiLabs bootloader encryption keys.
As presented to the user, the lockbits page is the same size as the other pages, but any attempt to write to its low 512 bytes is an error. To enforce this, efr32x_write is renamed to efm32x_priv_write and a wrapper function is provided in its place. If the user erases the lockbits page, the driver rewrites the cached lock words after the erase. When the driver erases the lockbits page in order to update the lock words, it first takes a copy of anything stored in the top part of the page, and re-programs it after the erase operation.
There are now multiple instances of flash_bank for each target, and the flash_bank instances must share their cached lock words to operate as intended. Therefore, when a bank is created, the global flash bank list is used to find any other banks that share the same target. Since some banks in the global list are invalid at the time free_driver_priv is called, reference counting is used to decide when to free driver_priv.
To avoid the need to find the lockbits flash_bank from another flash_bank, efm32x_priv_write and efm32x_erase_page now take an absolute address.
There didn't seem to be any reason to prohibit unprotecting individual flash pages, so that limitation is removed from efm32x_protect().
This addresses ticket #185.
Valgrind-clean, except for 2x 4kiB not freed/still reachable blocks that were allocated by libudev.
No new Clang analyzer warnings, no new sanitizer warnings.
Signed-off-by: Doug Brunner <doug.a.brunner@gmail.com>
Change-Id: Ifb22e6149939d893f386706e99b928691ec1d41b
Reviewed-on: https://review.openocd.org/c/openocd/+/6665
Tested-by: jenkins
Reviewed-by: Fredrik Hederstierna <fredrik.hederstierna@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This board is (software wise) similar to the existing SAME54 Xplained
Pro board, with just a slightly different MCU. (Hardware wise, it
features a vastly different form factor.)
Signed-off-by: Jörg Wunsch <openocd@uriah.heep.sax.de>
Change-Id: I5e5435d49d333fb74471994ee84de59ed983153c
Reviewed-on: https://review.openocd.org/c/openocd/+/6747
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Axel W.
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The stm32mp13x has one core Cortex-A7.
The board Discovery Kit includes an on-board STLink-V3 with SWD
connection.
The webpage of the board is not active yet.
Change-Id: I8836b26612a160ead79766955ebefaf3d21a329c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6675
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
The driver hla defines the command 'hla_serial' to specify the
serial string of the adapter.
The driver st-link defines the command 'st-link serial' to specify
the serial string of the adapter.
Remove and deprecate the driver commands and use 'adapter serial'.
Change-Id: I9505c398a77125b1ebf4ba71da7baf4d663b75be
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6657
Tested-by: jenkins
The driver jlink defines the command 'jlink serial' to specify the
serial string of the adapter.
Remove and deprecate the driver command, and use 'adapter serial'.
Note: in former code the commands 'jlink serial' and 'jlink usb'
were mutually exclusive; running one of them would invalidate the
effect of a previous execution of the other. The new code gives
priority to 'adapter serial', even if executed before 'jlink usb'.
Change-Id: I920b0c136716f459b6fd6f7da8a01a7fa1ed389f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6656
Reviewed-by: zapb <dev@zapb.de>
Tested-by: jenkins
The driver xds110 defines the command 'xds110 serial' to specify
the serial string of the adapter.
Remove and deprecate the driver command, and use 'adapter serial'.
Note: the original command 'xds110 serial' used a complex and
undocumented conversion of the serial number through multibyte
string, wide-character string and C cast. The XDS110 I can access
and the lsusb dumps available through Google don't show any
exotic USB serial that require such conversion. The original
developer doesn't remember any constraint that mandates such
conversion (see comments in https://review.openocd.org/4322/).
The conversion is removed by this patch.
Change-Id: I38909918079b2c1797ad85ebec2fea1b33743606
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6655
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
The driver kitprog defines the command 'kitprog_serial' to specify
the serial string of the adapter.
Remove and deprecate the driver command, and use 'adapter serial'.
Change-Id: I844cb815af01137392b6d12e1b5972fc77ac092d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6652
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
The driver ftdi defines the command 'ftdi serial' to specify the
serial string of the adapter.
Remove and deprecate the driver command, and use 'adapter serial'.
Change-Id: Ia5b1f325b9fab8f58b5ea70f8b807e50b148b939
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6651
Tested-by: jenkins
The driver cmsis_dap defines the command 'cmsis_dap_serial' to
specify the serial string of the adapter.
Remove and deprecate the driver command, and use 'adapter serial'.
Change-Id: I88e2d4de360a6c6f23529bb18494962a267250df
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6649
Tested-by: jenkins
The driver aice defines the command 'aice serial' to specify the
serial string of the adapter, but actually does not use this value
in the code.
Remove and deprecate the driver command, and use 'adapter serial'.
Change-Id: I892e0a4e1b41a7a87adf54a5736abf7419f32979
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6648
Tested-by: jenkins
GD32E23x from GigaDevice is cortex-M23 microcontroller and it can work with the stm32f1x driver.
Modifications are similar to this done for GD32F1x0 in #6164 (https://review.openocd.org/c/openocd/+/6164).
Configuration file is added because its cortex-M23 CPU ID is different.
I think that GigaDevice microcontrollers should be handled in an independent unit to separate them from STM32,
but nowadays quick solution is welcome.
Signed-off-by: asier70Andrzej Sierżęga <asier70@gmail.com>
Change-Id: I91f31f5f66808bc50a8f607ac2c107e6b7c5e2b8
Reviewed-on: https://review.openocd.org/c/openocd/+/6527
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Freeze the IWDG watchdog when cores are halted to prevent a reset
while debugging.
The PMIC present on some board senses the nsrst and forces a power
cycle to the target. The power cycle causes the SWJ-DP to restart
in JTAG mode. If the debugger is using SWD, the mismatch triggers
an error after the reset command.
Ignore the error detected by 'dap init' and proceed executing the
handler. The error in 'dap init' will force a reconnect during the
following 'dap apid', restoring the SWD functionality.
Change-Id: I04fcda6a5b8a1b080ab4e8890ecd0754d5ed12d9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6599
Tested-by: jenkins
Add the 0x3754 PID used by some STLINK-V3 devices when MSD has been
disabled. This PID has been observed on a Nucleo-G431RB board.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Change-Id: Idb85874fa5a9dff5940bae7e95426a956693b976
Reviewed-on: https://review.openocd.org/c/openocd/+/6555
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
do not force the presence of the reset line, since some custom boards
may do not contain the reset line.
Change-Id: I031ab34012b34a1b49def9db16461f9de0ae29cc
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reported-by: Fleck <fleckz@users.sourceforge.net>
Fixes: https://sourceforge.net/p/openocd/tickets/316/
Reviewed-on: https://review.openocd.org/c/openocd/+/6506
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
known boards are NUCLEO-G431KB, NUCLEO-G431RB and NUCLEO-G474RE
note: this work safely with B-G431B-ESC1, B-G474E-DPOW1,
STM32G474E-EVAL and STM32G484E-EVAL
Change-Id: I132a97e1816620b182983edc8a4b272b52b9241d
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5484
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
known boards are NUCLEO-G031K8, NUCLEO-G070RB, NUCLEO-G071RB
note: this work safely with STM32G0316-DISCO, STM32G071B-DISCO
and STM32G081B-EVAL
Change-Id: I483b6f44409228cd8c2c97b3c560927d1645c517
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5483
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
this device flash registers are quite similar to STM32L5
with this changes :
- flash size is up to 2MB
- 2MB variants are always dual bank
- 1MB and 512KB variants could be dual bank (contiguous addressing)
depending on DUALBANK bit(21)
- flash data width is 16 bytes (quad-word)
Change-Id: Id13c552270ce1071479ad418526e8a39ebe83cb1
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6108
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
according the RM0453, the second core have a different Flash CR and SR
registers for flash operations (called C2CR and C2SR).
so we need to a different flash_regs than older L4 devices.
@see stm32wl_cpu2_flash_regs
the C2CR register don't contain LOCK and OPTLOCK bits, and this explain
the addition of new register index called STM32_FLASH_CR_WLK_INDEX to
look-up the CR with lock, to be used in locking/unlocking the flash.
note: DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,
to solve this read the UID64 (IEEE 64-bit unique device ID register)
Change-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6050
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
when RDP level is 0.5 the provided work-area should reside in non-secure RAM
to ensure that:
- add a hint in the driver level
- reduce the usage of secure RAM only when TZEN=1 and RDP is not 0.5
(check the target configuration file)
Change-Id: Idbf2325e609b84ef8480eefdb49a176fdf7e07c7
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6035
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Tested-by: jenkins
STM32L5 flash memory is aliased to 0x0C000000, this address mapping
is used for secure applications. (0x08000000 for non-secure)
this change allows the programming of secure and non-secure flash
when trustzone is enabled and RDP level is 0
Change-Id: I89d1f1b5d493cf01a142ca4dbfef5a3731cab96e
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5936
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Add support for ECP5 FPGA targets and board based on this chips:
Radiona ULX3S and Lambdaconcept ECPIX-5
Change-Id: I932fc6e2458cda7d63ac21579acddea5b53410bc
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6112
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Sean Anderson
Antonio Borneo
Nishanth Menon
Tarek BOCHKATI
Jacek Wuwer
Hans-Erik Floryd
Doug Brunner
Joerg Wunsch
asier70
Andreas Sandberg
Marc Schink
Wealian Liao
Oleksij Rempel
Ranjith Chandran