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7713 Commits

Author SHA1 Message Date
mwachs5 bdc38561c0 riscv: Clean up reset/dmactive/step compliance test 2017-07-05 17:54:55 -07:00
mwachs5 2b94888100 riscv: Add single-step, reset, and dmactive to the compliance test. 2017-07-05 15:11:40 -07:00
mwachs5 87abbe4a51 Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2017-07-05 11:02:30 -07:00
Tim Newsome 321619946b Merge pull request #73 from riscv/old_triggers 
Add back support for type 1 triggers
 2017-07-03 13:52:16 -07:00
Palmer Dabbelt 3cff4213a4 Merge pull request #69 from riscv/multi-gdb 
Fix the multi-GDB mode bugs
 2017-07-03 13:18:06 -07:00
Palmer Dabbelt ce48a5d3da Merge pull request #72 from dmitryryzhov/examine_restore_temp_reg 
Restore value of temporary register (s0) in examine OpenOCD procedure…
 2017-07-03 12:43:47 -07:00
Tim Newsome f18fd83ac7 Fix trigger set/clear bug. 2017-07-03 11:52:35 -07:00
Tim Newsome 6c627e9ea9 Add back support for type 1 triggers. 
They were implemented, and people want to keep using them.
Also make OpenOCD tolerate cores that have $misa at 0xf10 instead of the
current address of 0x301.
Actually return an error when we fail to read a CSR.
Tweak cache_set32() debug output.
 2017-07-03 11:01:10 -07:00
Dmitry Ryzhov 99a3673507 Fix comment about saving the temporary register in examine procedure. 2017-07-01 15:09:23 +03:00
Dmitry Ryzhov 7d451e00f5 Restore value of temporary register (s0) in examine OpenOCD procedure in case of core can not execute 64 bit instruction. 2017-06-30 19:15:58 +03:00
Megan Wachs 8dc3c0a55c riscv: correct libjaylink version 2017-06-28 19:44:18 -07:00
Megan Wachs 7bc23c7776 riscv: Add some comments on what else compliance test needs 2017-06-28 19:36:22 -07:00
Megan Wachs 434fb3708a riscv: Correct DPC masking in compliance test. 2017-06-28 19:36:22 -07:00
Megan Wachs e32a8c911d riscv: Fix AUTOEXEC test for 32-bit cores 2017-06-28 19:36:22 -07:00
mwachs5 4101740928 riscv: add compliance tests for DPC and DCSR 2017-06-28 19:36:22 -07:00
mwachs5 e17ca3a31d riscv: More compliance tests for core registers. 2017-06-28 19:36:22 -07:00
mwachs5 222850df55 debug: add a 'wfi' to compliance test. 2017-06-28 19:36:22 -07:00
mwachs5 9e76ec1779 riscv: Compliance test for HALTREQ/RESUMEREQ R/W 2017-06-28 19:36:22 -07:00
mwachs5 ccc605158a riscv: Added several compliance test items 2017-06-28 19:32:38 -07:00
mwachs5 95ee7975ea riscv: Add skeleton of RISC-V v013 compliance 2017-06-28 19:32:38 -07:00
Megan Wachs 7a4948c126 riscv: initial checkin of a 'compliance test' command. 2017-06-28 19:32:38 -07:00
Tim Newsome b6f8efbf44 Check for errors in read_csr(). 
Also slightly improve debugging output.
 2017-06-27 15:11:06 -07:00
Palmer Dabbelt d77c4a953c Don't set breakpoints on disabled harts 2017-06-21 12:25:20 -07:00
Palmer Dabbelt 689d0fcaf6 No longer hard-code the non-RTOS hart to 0 
I was just being lazy here.
 2017-06-21 12:25:19 -07:00
Palmer Dabbelt 4bdb042224 Allow memory writes to proceed on all harts 2017-06-21 12:25:19 -07:00
Palmer Dabbelt a277416a39 Refactor examine, to avoid some assertions 
Now that we're supporting non-RTOS multi-hart mode there's some more
assertions that you're running on the right hart.  Those assertions
aren't sane very early in examine, so I avoid them.
 2017-06-21 12:25:19 -07:00
Palmer Dabbelt 788908fcf0 Factor out checking if harts should be used 
Rather than having a bunch of "if rtos" stuff, I now just check "if
hart_enabled".  This makes some code paths cleaner, all of which were
buggy in the non-RTOS multi-hart mode.
 2017-06-21 10:09:16 -07:00
Palmer Dabbelt 9f4cac5a38 Set current_hartid from coreid 
This avoids a bunch of RTOS special cases.
 2017-06-20 17:19:05 -07:00
Palmer Dabbelt 4e2e730abe Merge pull request #68 from riscv/multicore 
Testsuite now passes on multicore target
 2017-06-20 14:20:00 -07:00
Tim Newsome 9cd98058a0 Set hardware triggers on all harts. 
Right now we're using "threads" to represent harts. gdb/OpenOCD assume
there's only one set of hardware breakpoints among all threads. Make it
so.
 2017-06-20 13:10:35 -07:00
Tim Newsome 10518351bb Don't immediately segfault with -rtos on v0.11. 2017-06-20 11:32:42 -07:00
Tim Newsome ccdd26e3ef Comment curious code. 2017-06-20 11:32:42 -07:00
Tim Newsome 927f9d8873 Update list of "threads" when harts are discovered. 
This ensures that "info threads" is accurate as soon as gdb connects.
Also print out number of triggers that is discovered in examine().
 2017-06-20 11:32:42 -07:00
Tim Newsome 8d79a7c18b Merge pull request #67 from riscv/cosmetics 
Various cosmetic improvements
 2017-06-20 11:32:17 -07:00
Tim Newsome 4d264b3579 Put early DEBUG notice of XLEN back. 2017-06-19 08:46:02 -07:00
Tim Newsome 6082f35a55 Update debug_defines. Clarify debug output. 
Update debug_defines from the spec, commit 920ec9a690.
Decode dmstatus scans in the debug output.
 2017-06-16 14:02:25 -07:00
Tim Newsome fd81f7fcac Fix comment. 2017-06-16 14:02:25 -07:00
Tim Newsome 851849a295 Tell the user about detected harts. 2017-06-16 14:02:25 -07:00
Tim Newsome 3abb347bd9 Tighten up debug output. 
Assuming the program allocating code works, we don't need its output.
Only output parts of the debug RAM that are actually doing something.
 2017-06-16 14:02:25 -07:00
Tim Newsome 91c3dcc197 Merge pull request #66 from riscv/whitespace 
Fix indentation to match OpenOCD style.
 2017-06-16 13:07:46 -07:00
Tim Newsome ac2da40f74 Fix indentation to match OpenOCD style. 
This change is just in the whitespace. There are no code changes.

See http://openocd.org/doc-release/doxygen/stylec.html
 2017-06-15 12:44:50 -07:00
Tim Newsome 363a0a2bf2 Merge pull request #64 from riscv/release-fixes 
Two fixes from the release branch
 2017-06-15 12:43:46 -07:00
Palmer Dabbelt e17f8f03b5 Merge pull request #65 from riscv/print64 
Fix print statements to work with 64-bit addresses
 2017-06-15 12:35:07 -07:00
Tim Newsome 50a223ef9a Fix print statements to work with 64-bit addresses 2017-06-15 12:24:37 -07:00
Palmer Dabbelt afc9eb6c47 Jump to the RTOS hartid after halting 
When I disappeared the polls everywhere I forgot to sanitize the hartid
after halting.  This is an invariant that GDB expects: when you return
from a halt whatever thread is marked as currently selected is the
thread that the next register accesses reference.
 2017-06-15 12:16:33 -07:00
Palmer Dabbelt 099a3020d2 Clear abstract errors from register_read_direct 2017-06-15 12:16:24 -07:00
Palmer Dabbelt 1a69308621 Merge pull request #63 from riscv/crc64 
Accept 64-bit addresses in CRC requests.
 2017-06-15 12:15:49 -07:00
Tim Newsome 503da094e8 Accept 64-bit addresses in CRC requests. 2017-06-15 10:44:37 -07:00
Palmer Dabbelt ecc181d12d Merge pull request #62 from riscv/riscv64 
Merge mainline OpenOCD
 2017-06-14 17:02:04 -07:00
Tim Newsome 64af052911 Fix the build. 
Main change is to make riscv_addr_t be unsigned. The rest is mechanical
fixing of types, print statements, and a few signed/unsigned compares.

Smoketest indicates everything is working more or less as before.
 2017-06-13 12:33:01 -07:00