Commit Graph

11305 Commits

Author SHA1 Message Date
Parshintsev Anatoly bb7852646e add diagnostics for non-implemented data watchpoints
Change-Id: If5031c6d8cea1bfcc34bb65fd766f232498ed7ea
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-02 08:56:19 +03:00
Tim Newsome ee5c5c292f
Merge pull request #895 from kr-sc/kr-sc/reset-fails-with-assert
target/riscv: OpenOCD fails with assert during running "reset" command
2023-08-01 09:10:41 -07:00
Kirill Radkin 16e4096c00 target: OpenOCD fails with assert during running "reset" command
OpenOCD fails in the presence of inactive/unresponsive cores

I faced with case when inactive core returns 0 while reading dtmcontrol.
This leads to failure on assert: "addrbits != 0" in "dbus_scan".

Also change "read_bits","poll_target" funcs to avoid a lot lines in logs

Change-Id: If852126755317789602b7372c5c5732183fff6c5
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-07-31 19:27:51 +03:00
Tim Newsome c07d9251aa
Merge pull request #884 from riscv/from_upstream
Merge up to a3ed12401 from upstream.
2023-07-31 06:58:52 -07:00
Tim Newsome 1997e68dcb
Merge pull request #875 from zqb-all/support_multiple_DMs
target/riscv: support multiple DMs
2023-07-27 08:44:34 -07:00
Mark Zhuang a9f28dafd7 target/riscv: support check dbgbase exist
Change-Id: I0d65bf9b33fb6d10c33f4f038045832594579e58
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 14:31:11 +08:00
Mark Zhuang 80a8aa9e19 target/riscv: support multiple DMs
Support assign DMI address of the debug module by pass
-dbgbase to the target create command

Change-Id: I774c3746567f6e6d77c43a62dea5e9e67bb25770
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 01:06:44 +08:00
Mark Zhuang 895185caff target/riscv: add dm layer
prepare for support multiple DMs

Change-Id: Ia313006376e4fa762449343e5522b59d3bfd068a
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 01:06:38 +08:00
Tim Newsome aeb37cb461
Merge pull request #882 from MarekVCodasip/target-logging-usage
target/riscv: Add target name logging to most log prints.
2023-07-24 08:59:06 -07:00
Marek Vrbka 9036f4003a target/riscv: Add target logging to most logging instances
This patch adds target logging to logging instances where it makes sense.
This is especially useful when debugging multiple targets at once,
such as multicore systems.

Change-Id: Ia9861f3fa0e6e5908b683c2a8280659c3c264395
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-07-24 08:03:32 +02:00
Tim Newsome 21fd3e1d6c
Merge pull request #885 from erhankur/fix_tool_warnings
Fix Checkpatch and Sparse tool warnings
2023-07-21 09:12:55 -07:00
Erhan Kurubas 617f62a476 target/riscv: fix semantic checker warnings
Besides checkpatch, now upstream codes are scanning with
Sparse semantic checker tool.
This commit addresses some Sparse and checkpatch warnings.

Change-Id: I0e3e9f15220d8829c5708897af27aa86a8f90c07
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2023-07-20 23:09:06 +02:00
Erhan Kurubas e6f30aef80 src: fix clang15 compiler warnings
Below warnings are fixed.

1- A function declaration without a prototype is deprecated in all
versions of C [-Werror,-Wstrict-prototypes]

2- error: variable set but not used [-Werror,-Wunused-but-set-variable]

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I1cf14b8e5e3e732ebc9cacc4b1cb9009276a8ea9
Reviewed-on: https://review.openocd.org/c/openocd/+/7569
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-07-20 23:09:06 +02:00
Tim Newsome 1a089d8409
Merge pull request #888 from MarekVCodasip/ci-run-spike64-if-spike32-failed
github/ci Make Spike64-2 tests run regardless of Spike32 tests result
2023-07-20 12:09:20 -07:00
Tim Newsome c1cce47933
Merge pull request #886 from erhankur/update_espressif_chips
Update espressif chips
2023-07-20 12:06:59 -07:00
Tim Newsome fba957ab8e
Merge pull request #891 from riscv/cache_master
Run spike tests on `riscv` branch.
2023-07-19 11:15:29 -07:00
Erhan Kurubas 79bcab76a0 tcl/board: add Espressif board configs with builtin usb jtag
Board config files, to allow communication with
the builtin USB-JTAG adapter.

Change-Id: I80fb0c36b3cc164940ff266f1eaa287d870da94d
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2023-07-19 00:11:47 +02:00
Erhan Kurubas f21bd77dd1 tcl/target: add Espressif riscv targets (ESP32-C6, ESP32-H2)
ESP32-C6 and ESP32-H2 are single core riscv targets.

Change-Id: If92429de4fb67a040f303a54177d61b70e1ea281
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2023-07-19 00:11:42 +02:00
Erhan Kurubas c7500f9161 tcl/target: update esp32c2.cfg to reference shared functions in the esp_common.cfg
This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.

Change-Id: I825dd4fddb88e5514429d49ab13869ee6b9a28fc
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2023-07-19 00:11:37 +02:00
Erhan Kurubas cd36a25865 tcl/target: update esp32c3.cfg to reference shared functions in the esp_common.cfg
This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ie3413d3149388b17bc0199409ce86d3eb7cf5ee2
2023-07-19 00:11:33 +02:00
Erhan Kurubas 28446139da tcl/board: add esp32s3-builtin.cfg file
Board config file for ESP32-S3, to allow communication with
the builtin USB-JTAG adapter.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I1310f5db30f7df38fe9344f7ba2334611b53863e
Reviewed-on: https://review.openocd.org/c/openocd/+/7749
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-07-19 00:11:28 +02:00
Erhan Kurubas 5d78bc8ba6 tcl/interface: add Espressif builtin usb_jtag config file.
This config file enables communication over USB-JTAG with
ESP32-C3, ESP32-S3, ESP32-H2 and ESP32-C6 chips

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Iceea26972588d8c4919d1f3248684ece48ca9121
Reviewed-on: https://review.openocd.org/c/openocd/+/7748
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-19 00:11:22 +02:00
Erhan Kurubas ab2618d557 tcl/target: update esp32s3.cfg to reference shared functions in the esp_common.cfg
This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ifb0122f3b98a767f27746409499733b70fb7d0e8
Reviewed-on: https://review.openocd.org/c/openocd/+/7747
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-19 00:11:17 +02:00
Erhan Kurubas 01612de6ce tcl/target: update esp32s2.cfg to reference shared functions in the esp_common.cfg
This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I36c86fe4ebc99928ce48a5bff8cb9580a0fa3ac0
Reviewed-on: https://review.openocd.org/c/openocd/+/7746
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-19 00:11:12 +02:00
Erhan Kurubas faf67b9e12 tcl/target: update esp32.cfg to reference shared functions in the esp_common.cfg
This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I9181737d83eeba4e983b6a455b8a1523f2576dd2
Reviewed-on: https://review.openocd.org/c/openocd/+/7745
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-07-19 00:10:57 +02:00
Erhan Kurubas d64f490f22 tcl/target: move Espressif shared functions to esp_common.cfg
Consolidate commonly used commands and variables from
chip config files into functions in esp_common.cfg.
This includes "jtag newtap," "target create,"and "configure -event."
Enhances code reusability and simplifies maintenance.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I9e8bf07a4a15d4544ceb564607dea66837381d70
Reviewed-on: https://review.openocd.org/c/openocd/+/7744
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-19 00:10:35 +02:00
Tim Newsome ee0a8605ea Run spike tests on `riscv` branch.
The main reason is to populate the cache, so that pull requests can
benefit from a spike cache even the very first time. (Caches populated
in one pull request are inaccessible to another one.)

Change-Id: If894f2ccfaadc740bd52e34be3024153626b9fbd
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-07-18 11:08:17 -07:00
Tim Newsome fb284475a8
Merge pull request #878 from en-sc/en-sc/trigg-eq-check
target/riscv: cleanup trigger setup
2023-07-18 09:32:37 -07:00
Marek Vrbka deb0d918e2 github/ci Make Spike64-2 tests run regardless if Spike32 tests result
This patch separates the Spike tests into their own jobs and makes them run
regardless of the results of the previous test. Previously, if Spike32
tests failed, Spike64-2 tests did not even run. This can be an issue if new
tests are added in the riscv-tests repository which are not yet passing
on riscv-openocd.

Change-Id: I0bdaee5fbbba5582babab40f176cfab49660c246
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-07-18 14:48:31 +02:00
Evgeniy Naydanov a8f28fdd48 target/riscv: cleanup trigger setup
* Add a warning when eq trigger is setup and it's behavior is different
from other triggers.

* Make eq trigger's behavior consistent with other triggers in case of
length == 1.

* Fix a bug in setting chained triggers (LT, GT case).

* Improve logging.

Change-Id: Id1ed0d11971b8ed875afbb979e6c8a8b51dd3818
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-07-17 20:41:01 +03:00
Tim Newsome b67b80c6ac
Merge pull request #879 from riscv/power_dance3
target/breakpoints: Clear software breakpoints from available targets
2023-07-17 09:30:41 -07:00
Tim Newsome 814a3b5e7b
Merge pull request #871 from en-sc/en-sc/fix-mdx-err
target/riscv: refactor read_memory_progbuf()
2023-07-17 09:30:11 -07:00
Evgeniy Naydanov 8d660ea98d target/riscv: refactor read_memory_progbuf()
There were a couple of problems with previous implementation:

* Misalligned read would return ERROR_OK and print all zeroes.

* CMDERR_BUSY for abstract access was improperly handled:

According to the spec, no assumptions can be made about DM_DATA*
contents in such a case, but these were considered valid values from
memory.

* A fallback to one element read was implemented when DMI_STATUS_BUSY
occurred during batch reads, even though this can be accounted for.

Change-Id: I09174c61c951b2bb97a529b7f0aa5afaa995179b
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-07-14 22:23:02 +03:00
Tim Newsome 8032b78775
Merge pull request #883 from zqb-all/update_macro
target/riscv: update some macro
2023-07-14 10:23:07 -07:00
Mark Zhuang d5425c253c target/riscv: dynamic allocate memory for hawindow
Change-Id: Id2f1a2568a39eec0a9dd4fe0f155619b11f9d6ba
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-14 00:07:47 +08:00
Mark Zhuang 04d8cfc48c target/riscv: update some macro
1. update RISCV_MAX_HARTS to 2^20 according to SPEC
2. remove RISCV_MAX_REGISTERS, it's not used anywhere anymore
3. add parentheses

Change-Id: Iadf0fa1ba3bbe5b9420b8430883e140db87f4f9e
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-14 00:07:44 +08:00
Tim Newsome 674911ef18 Merge commit 'a3ed12401b1f7d9578fb7da881d3504e07acfc27' into from_upstream
Conflicts:
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c

Change-Id: I65bdb4d28c91e9022ce811de976c9bf474a0b590
2023-07-12 16:32:38 -07:00
Tim Newsome 122c54b4c2 target/riscv: Message when harts become available.
Change-Id: I3824e215a845ba7df3c7887ce1693378fde94b4b
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-07-12 16:17:43 -07:00
Tim Newsome 39a4f37f84 target/breakpoints: Clear software breakpoints from available targets
If a target where a software breakpoint was set is not currently
available, but there are other targets in the same SMP group that are
available, then we can use those to remove the software breakpoint.

Change-Id: I9faa427c7b3aee31504e6e6599539e6f29b58d8f
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-07-12 16:17:40 -07:00
Tim Newsome 162cc1e79d target/riscv: Fix typo in gdb_regno_cacheable() comment.
Change-Id: If8806853d47779b5b208202803ed5da437f7b624
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-07-06 10:40:59 -07:00
Tim Newsome 8fdce4534f rtos/hwthread: Call rtos_free_threadlist() again.
I think this was incorrectly removed in a merge.

Change-Id: I49fce230f35ae7bd368d2ed780c6c1ffe5939fda
2023-07-06 10:40:28 -07:00
Tim Newsome 21d21408aa
Merge pull request #872 from aap-sc/aap-sc/smp_manipulation
[target/riscv] support for smp group manipulation
2023-07-06 09:10:11 -07:00
Tim Newsome d963f886d4
Merge pull request #876 from MarekVCodasip/tdata-register-setting-fix
target/riscv: Fix the trigger writing sequence
2023-07-06 09:09:38 -07:00
Marek Vrbka ea115917b9 target/riscv: Fix the trigger writing sequence
According to section 5.6 in the RISC-V debug specification, the previous
way to set triggers was incorrect, as was discussed as part of
https://github.com/riscv/riscv-openocd/issues/870. This commit fixes the
sequence to be in line with the specification as well as adds some comments
to clarify for any future reader as to what is actually done.

Change-Id: Iffc5cc0f866a466a7aaa72a4c53ee95c9080ac9d
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-07-04 12:04:02 +02:00
Parshintsev Anatoly 2903daa9f1 [target/riscv] support for smp group manipulation
this functionality allows to query if a target belongs to some smp group
and to dynamically turn on/off smp-specific behavior

Change-Id: I469453d95e7c1640a91bc60d80c854404e508535
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-07-03 17:28:40 +03:00
Tim Newsome 92c0319261
Merge pull request #873 from eosea/bscan_tunnel_seg_fault_fix
Add null pointer check before right shift for bscan tunneling.
2023-06-29 10:09:12 -07:00
Tim Newsome 4be6a5683f
Merge pull request #874 from zqb-all/fix_haltgroup_supported
target/riscv: fix haltgroup_supported to info->haltgroup_supported
2023-06-27 10:08:53 -07:00
Mark Zhuang 34418ed1c8 target/riscv: fix haltgroup_supported to info->haltgroup_supported
Change-Id: Id1276aecd3097d90e035bf3808e0c472188ba474
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-06-27 15:46:23 +08:00
eolson 9d23d3774a Add null pointer check before right shift for bscan tunneling.
Change-Id: I5d4764c777f33d48705b3e5273eb840c13cfbfb7
Signed-off-by: eolson <erin.olson@seagate.com>
2023-06-22 13:11:15 -05:00
Chao Du a45589d60a
rtos/FreeRTOS: solve some conflicting usage of thread id. (#865)
* rtos/FreeRTOS: solve some conflicting usage of thread id.

1.
There are some RISCV-specific usage of thread_id, which has conflict with upstream.
Some adaptions are made in this patch, to make sure OpenOCD is sending a clear thread list to gdb.

2.
Use freertos_read_struct_value for xSchedulerRunning.

Change-Id: I001a88a0c6d8eac98a389c0217b4897f28124840
Signed-off-by: Chao Du <duchao@eswincomputing.com>

* fix typo.

Change-Id: Id6546cc74de44bbee7e44b7cb29b769a2f35ec4a

* correct the data type.

Change-Id: I28c7e111e569d94ba5f6e1ae21745ddb34d4dd12

* changes as per the review comment.

Change-Id: Ica4c705a8f2657700dc27e24790287ca802480fd

* another macro replacement.

Change-Id: Ia9330fed32d917cf87804051ba1b8d6ac42cfb7b

---------

Signed-off-by: Chao Du <duchao@eswincomputing.com>
2023-06-22 09:05:29 -07:00