Commit Graph

501 Commits

Author SHA1 Message Date
Evgeniy Naydanov 8dbb1250f5 break from long loops on shutdown request
In loops that typically take longer time to complete, check if there is
a pending shutdown request. If so, terminate the loop.

This allows to respond to a signal requesting a shutdown during some
loops which do not return control to main OpenOCD loop.

Change-Id: Iace0b58eddde1237832d0f9333a7c7b930565674
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-01-09 12:36:05 +03:00
Parshintsev Anatoly aded275b70 rename dbgbuf to progbuf
Change-Id: I29e2192d5ce9d0f13010d8a09bd4ef50f5c8844b
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-12-22 11:35:23 +03:00
Parshintsev Anatoly 928f10a537 introduce execution status for riscv_program
Change-Id: I3b283b49dea88a6f3d2159be3c9f6c6da604aa9e
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-12-22 11:35:18 +03:00
Tim Newsome af786c0eca
Merge pull request #963 from kr-sc/kr-sc/no-free-triggers
When an attempt to set watchpoint fails because there is no free triggers OpenOCD reports "unknown error"
2023-11-17 09:18:44 -08:00
Tim Newsome 334f690f2a
Merge pull request #958 from riscv/set_field_get_field
target/riscv: Replace [sg]et_field macros with functions.
2023-11-16 15:22:57 -08:00
Kirill Radkin fee2e04d90 When an attempt to set watchpoint fails because there is no free triggers OpenOCD reports "unknown error"
Now it returns `resource not available`

Change-Id: Ifbbd468bdf62023850690eb96fe8a16f4114e915
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-11-16 17:18:22 +03:00
Tim Newsome 86b430b6b4 target/riscv: Replace [sg]et_field macros with functions.
Compilers are good at optimizing, and with functions it's abundantly
clear what all the types involved are. This change means we don't have
to be super careful about the type of values because of what the macro
might do to them that might cause overflow.

The only place where the return type matters is in printf-style
functions, and I made get_value32() for those cases where a change was
needed.

This should set the stage for simply copying the latest debug_defines.h
from the debug spec build again.

Change-Id: I5fb19d0cfc1e20137832a7b344b05db215ce00e1
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-11-15 11:12:09 -08:00
Tim Newsome 6de536bbb8
Merge pull request #961 from en-sc/en-sc/coreid-target-riscv
target/riscv: clarify usage of `coreid`
2023-11-13 09:45:58 -08:00
Tim Newsome 1ea0e9b426
Merge pull request #928 from AnastasiyaChernikova/triggers
target/riscv: cache requests to trigger configuration
2023-11-10 12:12:03 -08:00
Evgeniy Naydanov 5ec9938c61 target/riscv: clarify usage of `coreid`
By definition in `target/target.h`, `coreid` is not a unique identifier
of a target -- it can be the same for targets on different TAPs.

Change-Id: Ifce78da55fffe28dd8b6b06ecae7d8c4e305c0a2
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-11-10 13:11:12 +03:00
Marek Vrbka 2357237815 target/riscv: Replace watchpoint value mask comparison value with macro.
This patch replaces ~(typeof(watchpoint->mask))0 with
WATCHPOINT_IGNORE_DATA_VALUE_MASK. This improves
readability and moves the RISCV target in line with
other targets.

Change-Id: I15ac4d4ee76098b304d9b22f720911ba4329c190
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-11-09 10:11:22 +01:00
Tim Newsome f119c1d480
Merge pull request #954 from riscv/from_upstream
Merge commit '05ee88915520d1dd82da94a016a9374a1f3a8129' from upstream
2023-11-07 09:17:37 -08:00
Tim Newsome 5653f512a2
Merge pull request #952 from MarekVCodasip/stop-caching-dpc
target/riscv: Stop caching writes to DPC
2023-11-07 09:04:58 -08:00
Anastasiya Chernikova fea20e2bf5 target/riscv: cache requests to trigger configuration
Depending on configuration, the existing implementation of watchpoints is
rather inefficient for certain scenarios. Consider HW that:

1. triggers 0-3 can be used as instruction breakpoints
2. triggers 4-7 can be used as data breakpoints (watchpoints)
3.  NAPOT triggers are not supported.

Now, consider that we have a pending watchpoint. And we perform a "step"
operation. According to the current implementation:

* OpenOCD will disable watchpoints
* Perform a single-step
* Will try to restore the original watchpoints. It will need 12 attempts
to find a suitable trigger: (8 attempts to try NAPOT, and another 4 to try
GE+LE).

This patch introduces a dedicated cache for requests to triggers. It
significantly speeds things up, since we cache failed attempts and no
additional interactions with HW is necessary.

Change-Id: Ic272895eaa763a7ae84d14f7633790afd015ca9d
Signed-off-by: Anastasiya Chernikova <anastasiya.chernikova@syntacore.com>
2023-11-07 14:51:49 +03:00
Tim Newsome b5bd88441c Merge commit '05ee88915520d1dd82da94a016a9374a1f3a8129' into from_upstream
Conflicts:
	src/jtag/drivers/xds110.c
	src/target/riscv/riscv.c
	src/target/riscv/riscv_semihosting.c
	tcl/target/esp_common.cfg

Change-Id: If0c02817df03b7fd700cc84b4da2c02d36737d28
2023-11-06 09:25:46 -08:00
Tim Newsome c2f544c4f6 target/riscv: gdb_regno_name takes an enum.
Otherwise it won't compile for me. Not sure why that doesn't affect the
automated builds.

Change-Id: Ic66c743e1698c4c0772e5601723cb5c711b4fa5c
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-11-03 10:48:05 -07:00
Tim Newsome b75bfab026
Merge pull request #896 from AnastasiyaChernikova/ac-sc2
target/riscv: Adding register tables to make register names consiste
2023-11-03 10:30:35 -07:00
Tim Newsome 2676f05f2f
Merge pull request #947 from riscv/from_upstream
From upstream
2023-11-03 10:13:05 -07:00
Marek Vrbka adb9c3209e target/riscv: Stop caching writes to DPC
Since DPC is WARL (same rules as MEPC according to
the specification), it is possible that
writes to it won't result in the exact value present.
Therefore, writes to it shouldn't be cached, same as
with other WARL registers.

Change-Id: I818c0cef9727b999b7d84b19f9f42cd706c99d69
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-11-03 12:11:01 +01:00
Anastasiya Chernikova 805d394ff8 target/riscv: Adding register tables to make register names consistent
Added the ability to enter dimensionless registers

Change-Id: I1b781959ce4690ec65304142bd9a7c6f540b3e86
Signed-off-by: Anastasiya Chernikova <anastasiya.chernikova@syntacore.com>
2023-11-02 17:21:59 +03:00
Kirill Radkin 57c3f0d91c target/riscv: Fix memory access when MMU is enabled and address couldn't be translated
Now:
1) If mmu is disabled, virt2phys succeeded and returns physical address
2) If mmu is enbaled, but translation fails, read/write_memory fails

Change-Id: I312309c660239014b3278cb77cadc5618de8e4de
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-10-30 15:59:41 +03:00
Tim Newsome f02fe0960c Merge commit '9f23a1d7c1e27c556ef9787b9d3f263f5c1ecf24' into from_upstream
Conflicts:
	HACKING
	src/target/riscv/riscv-013.c

Change-Id: I43ccb143cae8daa39212d66a8824ae3ad2af6fef
2023-10-27 09:00:59 -07:00
Tim Newsome 2d98ef5d13
Merge pull request #941 from kr-sc/kr-sc/fix-hgatp-mode-upstream
hgatp_mode in riscv_virt2phys_v defined by vsatp value
2023-10-24 07:57:37 -07:00
Kirill Radkin 109772012a hgatp_mode in riscv_virt2phys_v defined by vsatp value
Replace `vsatp` with `hgatp` (how it should be)

Change-Id: Ie548467b06d1fb266ccc56cbec1aff8d9f435973
2023-10-23 18:56:40 +03:00
Tim Newsome 912de786a4
Revert "target/riscv: Reject size 2 soft breakpoints when C extension not supported" 2023-10-20 15:37:28 -07:00
Tim Newsome e1fa78d1b3
Merge pull request #929 from aap-sc/riscv
do not assume DTM version unless dtmcontrol is read successfully
2023-10-16 12:10:25 -07:00
Tim Newsome beb705912b
Merge pull request #917 from kr-sc/kr-sc/disable-triggers-option
provide riscv-specific controls to disable triggers from being used for watchpoints
2023-10-11 12:34:07 -07:00
liangzhen 3f1339f8e8 target/riscv: use cacheable read/write function to handle DCSR
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
2023-10-07 09:26:31 +08:00
Parshintsev Anatoly 2c4118ecea do not assume DTM version unless dtmcontrol is read successfully
Change-Id: I5f2003b7ac5ce87af6ca9a4fcb46140682a8cfdf
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-10-06 18:51:53 +03:00
Kirill Radkin e76a9b799d provide riscv-specific controls to disable triggers from beeing used for watchpoints
Add a new riscv specific commands to disable triggers

Change-Id: Ic1842085aa66851c740e0abcbfbe0adbe930920e
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-10-02 11:54:07 +03:00
Tim Newsome 75b5de67df
Merge pull request #918 from kr-sc/kr-sc/allow-to-query-status-dcsr-ebreak
openocd does not allow to query status of dcsr.ebreak{u,s,m}
2023-09-29 09:30:46 -07:00
Tim Newsome ef3be96ba1
Merge pull request #892 from en-sc/en-sc/register-printing
target/riscv: define register printers
2023-09-28 08:36:36 -07:00
Kirill Radkin ee2bc807eb openocd does not allow to query status of dcsr.ebreak{u,s,m}
Extend riscv set_ebreak* commands.
Now it can be called without args to print current value.

riscv_ebreak* flags are moved to riscv_info struct.

Change-Id: Ib46e6b6dfc0117599c7f6715c7aaf113e63bd7dc
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-09-26 11:52:30 +03:00
Evgeniy Naydanov 43ebdd47a5 target/riscv: define register printers
`riscv_debug_reg_to_s()` can be used to decode register value.  If the
pointer to buffer is `NULL` it does not print anything, just returns the
length of the string.

The format is:
`<register_value> { <field_name>=<field_value_name or field_value>, ..., }`

e.g:

`0x400382 { version=2, ... ndmresetpending=false, }`

`0x321009 { regno=0x1009, ... cmdtype=0, }`

Change-Id: I63733d8d36385d89ca15de1a43139134bc488c4f
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-09-22 16:26:28 +03:00
Tim Newsome 2c2135a0cb target/riscv: Don't assert in riscv013_get_register()
When the target isn't halted, simply return an error. This used to be
purely internal code so an assert was appropriate. Now after some
refactoring and with unavailable harts you could get here when the hart
is unavailable. In that case the right thing is simply to return an
error message.

Change-Id: I49d26a11fe7565c645fd2480e89a2c35ea9b1688
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-09-13 13:44:20 -07:00
Tim Newsome 42dcc99026
Merge pull request #909 from en-sc/en-sc/cleanup-enumerate-triggers
target/riscv: cleanup riscv_enumerate_triggers()
2023-09-08 09:21:55 -07:00
Evgeniy Naydanov c286f938f4 target/riscv: cleanup riscv_enumerate_triggers()
1. Propagate error codes.
2. Disable leftover triggers in case `tinfo` is supported.

Change-Id: Ie20edb4d8b9245e13ac8757bf6afe549ac99c4f1
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-09-07 13:39:50 +03:00
Marek Vrbka 8ad41767c0 target/riscv: Reject size 2 soft breakpoints when C extension not supported
This patch disables software breakpoints of size 2 for targets
which don't support compressed instructions.

Change-Id: I8200b22a51c97ba2aa89e6328beadde8dd35cdd5
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-09-04 07:47:03 +02:00
Tim Newsome 699eecaab4
Merge pull request #906 from MarekVCodasip/zero-no-cache
target/riscv: Don't write to zero.
2023-08-30 10:59:54 -07:00
Marek Vrbka 0b914fe5ae target/riscv: Don't write to zero.
During a previous patch, the ignoring of writes to register zero
was deleted. This patch restores it to the original.

Change-Id: Ieb028a5b2e3f691e4847713c7bc809e10726e18c
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-08-25 07:54:59 +02:00
Tim Newsome 928f2b374a
Merge pull request #904 from kr-sc/kr-sc/support-sv57
target/riscv: Add support for Sv57 (and Sv57x4) translation mode
2023-08-23 12:03:21 -07:00
Tim Newsome 9260101307
Merge pull request #899 from en-sc/en-sc/trig-handle-res-not-avlbl
target/riscv: improve error handling in trigger setup
2023-08-14 09:48:03 -07:00
Kirill Radkin 1d2eea0399 target/riscv: Add support for Sv57 translation mode (including second-stage translations)
Also fix Sv48x4 translation mode
2023-08-14 14:33:44 +03:00
Evgeniy Naydanov 9b558838b1 target/riscv: improve error handling in trigger setup
Change-Id: I235973a3c44fb3d934925c74ffee47f8bd96de0d
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-08-03 17:58:16 +03:00
Parshintsev Anatoly bb7852646e add diagnostics for non-implemented data watchpoints
Change-Id: If5031c6d8cea1bfcc34bb65fd766f232498ed7ea
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-02 08:56:19 +03:00
Tim Newsome c07d9251aa
Merge pull request #884 from riscv/from_upstream
Merge up to a3ed12401 from upstream.
2023-07-31 06:58:52 -07:00
Tomas Vanek a5108240f9 target: fix messages and return values of failed op because not halted
Lot of messages was logged as LOG_WARNING, but the operation failed
immediately. Sometimes no error message was logged at all.
Add missing messages, change warnings to errors.

Sometimes ERROR_TARGET_INVALID was returned. Some command handlers
returned ERROR_OK! Always return ERROR_TARGET_NOT_HALTED.

While on it use LOG_TARGET_ERROR() whenever possible.
Prefix command_print() message with 'Error:' to get closer
to LOG_TARGET_ERROR() variant.

Error message was not added to get() and set() methods of
struct xxx_reg_type - the return value is properly checked and a message
is logged by the caller in case of ERROR_TARGET_NOT_HALTED.

Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I2fe4187c6025f0038956ab387edbf3f461c69398
Reviewed-on: https://review.openocd.org/c/openocd/+/7819
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-29 05:17:44 +00:00
Mark Zhuang 895185caff target/riscv: add dm layer
prepare for support multiple DMs

Change-Id: Ia313006376e4fa762449343e5522b59d3bfd068a
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 01:06:38 +08:00
Marek Vrbka 9036f4003a target/riscv: Add target logging to most logging instances
This patch adds target logging to logging instances where it makes sense.
This is especially useful when debugging multiple targets at once,
such as multicore systems.

Change-Id: Ia9861f3fa0e6e5908b683c2a8280659c3c264395
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-07-24 08:03:32 +02:00
Erhan Kurubas 617f62a476 target/riscv: fix semantic checker warnings
Besides checkpatch, now upstream codes are scanning with
Sparse semantic checker tool.
This commit addresses some Sparse and checkpatch warnings.

Change-Id: I0e3e9f15220d8829c5708897af27aa86a8f90c07
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2023-07-20 23:09:06 +02:00