* WIP upstream review feedback.
See http://openocd.zylin.com/#/c/4656/
The main change is to get rid of macros that contain a return statement.
Change-Id: Iff79a8aa7c40ee04a8d1f07d973f9b29d4899d5c
* Remove unaligned head/tail code.
From inspection it's not clear to me that this is necessary at all. I've
been unable to make a test case that results in anything besides a
4-byte aligned flash to happen. Sections that aren't multiples of 4 are
common, and appear to work fine.
Change-Id: Idb6109ca015ae06b9d8f16bd883f9c8f5c51087d
* Move fespi native code into contrib/loaders
As suggested by http://openocd.zylin.com/#/c/4656/
Change-Id: I275012aa8a1ef6a0e8a2ec8ebe8643d87de24407
* Reenable hw mode if errors happen without it.
Change-Id: I1220033c13d02e8a441992bd6daa0ec3b5acbfca
* Default flash to not protected.
Requested by upstream review.
Change-Id: I61753bd9909d7f21ef6624037a865072c18bd1d8
Instead of trying to predict exactly how many steps will be required
(doable but error-prone), just allocate more memory when we need it.
Tested against HiFive1, and Arty board image.
Change-Id: I3cd9798432e65176616c700ba122daf7a5ed6209
Main change is to make riscv_addr_t be unsigned. The rest is mechanical
fixing of types, print statements, and a few signed/unsigned compares.
Smoketest indicates everything is working more or less as before.
This is a major rewrite of the RISC-V v0.13 OpenOCD port. This
shouldn't have any meaningful effect on the v0.11 support, but it does
add generic versions of many functions that will allow me to later
refactor the v0.11 support so it's easier to maintain both ports. This
started as an emergency feature branch and went on for a long time, so
it's all been squashed down into one commit so there isn't a big set of
broken commits lying around. The changes are:
* You can pass "-rtos riscv" to the target in OpenOCD's configuration
file, which enables multi-hart mode. This uses OpenOCD's RTOS
support to control all the harts from the debug module using commands
like "info threads" in GDB. This support is still expermental.
* There is support for RV64I, but due to OpenOCD limitations we only
support 32-bit physical addresses. I hope to remedy this by rebasing
onto the latest OpenOCD release, which I've heard should fix this.
* This matches the latest draft version of the RISC-V debug spec, as of
April 26th. This version fixes a number of spec bugs and should be
close to the final debug spec.
The target may have already configured its clock to run at a higher frequency and would have set SCKDIV and other dividers at that time. Don't restore the SCKDIV to its default or the flash interface may run too fast and programming will fail.
Otherwise, the default value is fine and there is no need to write SCKDIV.
If the working area is large enough, every fespi_write() results in just
a single algorithm execution.
Change-Id: I87a12e29f50ef6ea1f46fbd1edf440f9e54a2162
Tim Newsome
Megan Wachs
Palmer Dabbelt
Albert Ou