88f14f4d5e
Check busy before triggering another command.
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This version was able to download code, and run to a breakpoint.
Change-Id: I0ead8350579263d8e55f8df35e2b7af6c374ef21
2017-02-16 14:21:17 -08:00
ef3875a320
Check for errors after read/write.
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The code doesn't do anything intelligent if errors are found.
But MemTestBlock now also passes. I'm not quite sure why.
Change-Id: I8512f0a96db9e34d3db6a4a9bcef6e56f191d4c1
2017-02-15 20:41:39 -08:00
035b4dd17a
Fix double read, which might have side effects.
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Now passing MemTest{8,16,32,64}
Change-Id: I286d1e2a388d41853e5aa9049490ddb6135b61f1
2017-02-15 19:05:51 -08:00
713c001242
Make MemTest32 pass.
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Change-Id: I9be90b07be695c976380f9fd50b971f8bb94f513
2017-02-15 17:10:53 -08:00
79e840aaa7
Some memory access works.
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MemTest16 passes, but MemTest32 fails.
Change-Id: I17fbc38b4228b27c7fb3dadb15e9c1a2f67bcd65
2017-02-15 15:44:36 -08:00
657e844c8c
Merge pull request #15 from sifive/get_set_reg_error
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Use the set/reg register error return code when registers don't exist.
2017-02-14 17:28:10 -08:00
ceb8dc048d
Make general CSR reads work.
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Change-Id: Ic9b7e065b7303b3707c28c9b7c496cc1c1e91acd
2017-02-14 12:55:03 -08:00
ae4fda2719
Make it all the way through examine().
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This includes reading GPRs (although I haven't confirmed the values) and
doing some CSR reading/writing to disable triggers that may be left over
from a previous setting.
Change-Id: I2c627bd002d601e302a40f838087541897c025fd
2017-02-14 11:43:58 -08:00
00925574d5
More dbus->dmi.
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Change-Id: Ia691f1e7ce909da4d9c16e6d691c4f2cf768a7fb
2017-02-14 09:38:09 -08:00
24033b53d8
Read misa during examine(), using program buffer.
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Change-Id: Icad5324d216b61207cb5f6024b2deab065658640
2017-02-13 21:29:02 -08:00
0fa8162a8c
dbus -> dmi
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Change-Id: I4c3343f8f5ffd45e3d76a2218aaa5dee8e546839
2017-02-13 11:13:14 -08:00
e2a5e02d1c
Discover XLEN using abstract reg reads.
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Change-Id: Ib7480b8e4925cf08e5b59d263bcdcc672a89dc4b
2017-02-13 09:54:05 -08:00
e6221e75c9
Attempt to discover XLEN with abstract reg reads
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Change-Id: I7ce9c8c0c34bd875dba11596e6f6268320b2fb3a
2017-02-10 19:08:44 -08:00
3a1d6f1702
riscv: Add register name to message when they do not exist.
2017-02-10 14:19:23 -08:00
5e3d9803ab
Halt target in riscv_examine().
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Change-Id: I11ab915901f2e75f9b728d6cf72c6498e3950ded
2017-02-10 11:31:14 -08:00
075c0e80d1
Add debug_defines.h.
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Change-Id: I94753f9bed11cbc978daa0f3ea3ecf2023b93893
2017-02-09 09:57:54 -08:00
2ad366e658
Detect and smoketest data and ibuf registers.
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Change-Id: I7ee4817ec63041a1577b83392d40b676fb67c207
2017-02-08 20:40:37 -08:00
8cac7d0cee
Correctly parse dmcontrol.
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Change-Id: Ibae425f4ccbe9e504c41e185f264f667e091fca4
2017-02-08 19:47:34 -08:00
8af4a9a053
Update DMI bus width for 0.13.
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Change-Id: Ieff13a7a0084fe822b7cc6d927727eba4f158ef0
2017-02-07 11:28:50 -08:00
7b95554ff5
Merge remote-tracking branch 'origin/riscv' into HEAD
2017-02-07 11:24:12 -08:00
ecc5b6ecad
Add missing header file.
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Change-Id: I19df5112c2503ec6652f2d09e7324180af5024df
2017-02-05 21:32:44 -08:00
2ae0078fc7
Use the set/reg register error return code when registers don't exist.
2017-02-05 21:06:43 -08:00
6f78eb1ec1
Add the first difference for 0.13 targets.
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Just to confirm the 0.13 code takes a different path.
Change-Id: I7f1c9c8f3b586aee001dbeef2213f5f2e6a94f36
2017-02-05 18:21:34 -08:00
8d195afd2d
Use the csrNNN name instead of "mstatus".
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Fixes flashing code.
Change-Id: Id12c926f5ada009e06f6601362deefec946afc98
2017-02-05 18:19:00 -08:00
d055f86552
Most gdbserver tests pass now.
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Change-Id: I14a8360d9cf2800ca5e6a44f7e58102b2baef719
2017-02-05 18:09:19 -08:00
5d82a395f1
riscv: disable interrupts for all priviledge levels
2017-01-25 21:51:02 -08:00
d5892f0ee5
riscv: Use proper UINT packing and unpacking routines for disabling interrupts before running algorithms.
2017-01-25 15:23:10 -08:00
5766efe0c3
riscv: Globally disable interrupts when running algorithms.
2017-01-25 11:35:57 -08:00
4a0d3fb035
riscv: implement skeletons for Memory Blank Check and CRC. Otherwise you just get a segfault when attempting to perform these actions.
2016-12-07 15:09:35 -08:00
c1da323144
Fix issue #6 : build failure on gcc 6
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Change-Id: If890a6d62fdd55befb9057f83726f60721ac8078
2016-12-01 19:15:55 -08:00
7dd48acdc0
Cope better if the target unexpectedly resets.
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Change-Id: I713f7f8a3afbbb02be0e2f19f4d32778366d37f9
2016-11-25 09:46:55 -08:00
8ee0647365
Flash at 8KB/s, using 10,000 byte working area.
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If the working area is large enough, every fespi_write() results in just
a single algorithm execution.
Change-Id: I87a12e29f50ef6ea1f46fbd1edf440f9e54a2162
2016-11-18 10:58:26 -08:00
c406b4530e
Merge branch 'Og' into enable_flash_prog
2016-11-17 13:44:35 -08:00
18eedf996c
Use algorithm to speed up fespi flash programming.
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It's still really slow, at 854b/s, but it seems to work and it's a lot
of new code.
Change-Id: I9dd057bbcc81a56eb558b4f33ac35f6f03c23588
2016-11-16 17:54:55 -08:00
e51b0360f5
Make fpu regs work even if mstatus.fs is 0.
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Change-Id: I2c283f2de226518ab9a4e0476edada51825b2993
2016-11-01 12:58:37 -07:00
e7a745ed3b
Fix bug with slow targets.
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Halting didn't work right in slow targets, because some code assumed the
register cache is valid before it was guaranteed to be.
Also made dbus_busy_delay and interrupt_high_delay grow faster, so that
on slow targets it takes less time to learn the correct values.
Change-Id: I948a49d4e3cd0638f5449ab94994406319fd5f42
2016-10-27 13:00:26 -07:00
e6e2070692
Add some comments.
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Change-Id: Icd7d5eb370c6c893ec4717c92249f35fb100370a
2016-10-24 14:21:34 -07:00
3eb6cf0fc0
Make CLI step and resume work.
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Change-Id: I027d7032800f909e8d149ed84c11b6e75b75491f
2016-10-20 14:49:23 -07:00
9b0be80d1e
Use reg_cache structure, to make reg command work.
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Change-Id: I9f1d1f2eab66822c3c47284aa91b52cc34998381
2016-10-20 10:42:28 -07:00
4eba841bfe
Print when we're ready for gdb to connect.
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This should help gdbserver.py to connect reliably to really slow targets
(ie. simulators).
Change-Id: I8e9adbaf2ebde11b44e15582f036622a2d00c1f9
2016-10-14 12:40:52 -07:00
3f6c2a9f78
Be quiet when the target is just running normally.
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Change-Id: I7861f16ba6b1b5c1851787ce5d78c02aff0568f6
2016-10-13 10:51:53 -07:00
cb93bb9035
Use an easily changed constant for timeout.
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Change-Id: I7aace463b0bd9916580e950d60b2940879b27b2a
2016-10-11 16:26:19 -07:00
4882de94cc
Display pc to the user in 'monitor reset init'.
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Change-Id: Ifb8df31954dfc5a3badef4f0a29eb510a97310a2
2016-10-10 08:22:51 -07:00
80e8101292
Make OpenOCD build using -Og.
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With -Og gcc doesn't perform as many optimizations, and as a result
warns about some code that it wouldn't otherwise warn about.
These fixes all assign values to otherwise uninitialized variables.
Change-Id: I9a6ea5eadd73673891ecfec568b8b00d78b596a5
Signed-off-by: Tim Newsome <tim@sifive.com>
2016-10-04 10:02:42 -07:00
a08cef7633
Change invalid access from error to user message.
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It's not a failure in the debugger or even a real problem if a user asks
to access memory that's not accessible.
Change-Id: I30b8424d5265d1996fe4826012ed160a83f0bc6c
2016-10-03 08:15:04 -07:00
e273e23f41
Fix off-by-one error in assert.
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Also only do work for debug RAM that actually exists on the target
(exposing the off-by-one error on 32-bit targets).
Change-Id: I37e0005b6a70e949286f1d6494716f3abea03c12
2016-09-29 10:40:50 -07:00
4dbc9962d3
Clear dmode triggers when we first halt the target
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This helps repeated runs of the testsuite pass, and is probably a good
idea in general.
Change-Id: I89ed167968f8b8817c66f1718f374d0c502780c7
2016-09-29 10:23:46 -07:00
78fe0b56db
Deal with dbus being busy in all cases.
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Change-Id: Ifede6e05c3c4538f22a52cd0e9833cf3a9983d04
2016-09-29 08:28:31 -07:00
b04d5e8821
Read idle, and test all debug RAM.
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Read dtmcontrol's idle field to decide how many run-test/idle cycles are
required to communicate with the target.
In riscv_examine(), write and read all of Debug RAM to check the target
is at least somewhat sane.
Change-Id: Ieedb7a50418fa1f5e0d456cde53c52f7fc51662b
2016-09-27 13:06:32 -07:00
c67850b63d
Only write to existing dram. Clear dbus error.
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Old code would write 64 bytes of DRAM if the dbus was busy in
cache_write().
New code clears the dbus error condition when the bus is busy. (This
part is untested.)
Change-Id: Ia396fe819fa1828bb75726d85513b113cc9e13f0
2016-09-27 08:45:51 -07:00
Tim Newsome
Megan Wachs