This adds a trivial config for LPC8xx chips based on the already
existing infrastructure in lpc1xxx.cfg.
Change-Id: I7384df1f3c2e3e8ab767319728db5c4f8149480f
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2464
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
It depends on the particular target whether it can work with SRST
asserted or not, so this belongs to the target config rather than the
board config.
Also, this allows for simple
openocd -f myboard.cfg -c "reset_config connect_assert_srst"
command to be used whenever a user feels a need to connect to an
unresponsive target.
Change-Id: I3d8da9ae47088fc0c75a20bfdd20074be1014de0
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2459
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
So remove it from all the configs, it's misleading, and leads to cargo
culting of config files.
Change-Id: I2b77e60d5e96f9759c7c9fc91b20e73be2e95d9a
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2446
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This should have been corrected earlier with the split of l1/l0 code
apart.
Change-Id: I87b94a310ae7e76318554a9cd2705348a942d58b
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2447
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
L0 is cortex m0+, so different id codes, SWD only, different addresses
for the clock speedup. It has no endian options, no boundary scan.
Removed all L0 specific portions from L1 files, and renamed files to clarify
their purpose. The deprecated stm32lx_stlink.cfg is kept as is, as it is only
around for backwards compatibility with prior releases.
Tested on STM32L053 Discovery and STM32L151 Discovery.
Has _not_ been tested with jtag on L1.
Change-Id: I8eea890d2f92a302d9e9c8a8832d218ee1b6bcfc
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2405
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Juha Niskanen <juha.niskanen@haltian.com>
Fix script parse error, when using JTAG, introduced in
commit 0187ced9ed
Add several BS TAPIDs with comments about ST documentation.
Change-Id: I8d0370b244ccaf7ea0dbe1919bfad1915f7317d4
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
Reviewed-on: http://openocd.zylin.com/2376
Tested-by: jenkins
Reviewed-by: Rémi PRUD'HOMME <prudhomme.remi@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Since all F4 parts have an internal HSI providing 16MHz, it's safe to
use 2MHz JTAG frequency by default.
Change-Id: I2702d5a1d642d4acd4af2db54c028949132c6900
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2383
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add CPUTAPID for stm32 L0xx mcu devices. Using -expected-id to
add the new id with the id for L1xx devices. This for reduce the
duplicated code.
Change-Id: I48bd230884ecf38fa200c620b547bdf3b5f59132
Signed-off-by: Rémi PRUD'HOMME <prudhomme.remi@gmail.com>
Reviewed-on: http://openocd.zylin.com/2315
Tested-by: jenkins
Reviewed-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Remove this underutilized feature. Despite the fact that a lot of configs
specifies a arbitrary "variant", only the xscale target actually defines
any.
In the case of xscale, the use of -variant is dubious since
1) it's used as a redundant irlen specifier,
2) it carries a comment that it doesn't really need it and
3) only two xscale configs even specify it.
If there's a future target that needs a variant set, a target specific
option could be added when needed.
Change-Id: I1ba25a946f0d80872cbd96ddcc48f92695c4ae20
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2283
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Since now auto-detection for flash size works nicely, there's no
reason to keep numerous configs around.
Change-Id: If0cbc37985abf17ef7c1f7d0688e76500fac228f
Signed-off-by: Vanya Sergeev <vsergeev@gmail.com>
Reviewed-on: http://openocd.zylin.com/1960
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This adds config to allow JTAG debugging of an ARM core of a modern
hybrid SoC by Research Centre "Module"
(http://www.module.ru/en/company/). К1879ХБ1Я is targetted at set-top
boxes and other multimedia equipment, the official SDK is Linux-based.
Change-Id: Ib2ae5784d25699f952682e66b025a3f677a76d5d
Signed-off-by: Бурага Александр <dtp-avb@yandex.ru>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2272
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This is for mx6q TO1.1.
Change-Id: Id6af2ed232fc19be9bf49eb6d2df0004c6668698
Reported-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2253
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
According to Nordic Semiconductor Product Anomaly Notice (document
NRF51822-PAN), item 16, some revisions of nRF51822 sometimes reset
without all RAM blocks enabled. This was noted on NRF51822-QFAA rev
CA/C0, only 8KiB of memory was accessible.
This patch turns on all RAM following a debugger induced reset
(matches specified behaviour.)
Change-Id: I4f8be4ec3d1271da7fe5bc9a084fdcb2968535bb
Signed-off-by: Angus Gratton <gus@projectgus.com>
Reviewed-on: http://openocd.zylin.com/2202
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This should allow to share common configs for both regular access and
high-level adapters.
Use the newly-added functionality in stlink and icdi drivers, amend
the configs accordingly.
Runtime-tested with a TI tm4c123g board.
Change-Id: Ibb88266a4ca25f06f6c073e916c963f017447bad
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
[gus@projectgus.com: context-specific deprecation warnings]
Signed-off-by: Angus Gratton <gus@projectgus.com>
[andrew.smirnov@gmail.com: additional nrf51.cfg mods]
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Tested-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
Reviewed-on: http://openocd.zylin.com/1664
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
I looked through all the target configs after stripping comments and
such from them with sed to see what jtag-specific commands can appear
first, and it looks like all the meaningful combinations should be
covered.
Change-Id: I8d543407b7f4ac8aca7354ecd50e841c8a04d5f3
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2179
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
SAM4L requires additional steps to be taken right after SYSRESETREQ is
issued in order to function robustly:
- CMSIS-DAP DAP driver needs to explicitly check for sticky bit
errors since it is possible for adapter to perform successful
write opration, report no errors and then, under the hood, do
some other things that will result in sticky bit being set.
- Debugger needs to wait for security system to finish
intialization and assert CDBGPWRUPACK before proceeding
This change is related to commit http://openocd.zylin.com/#/c/1995/
Change-Id: I741c95a809bfd60d930cec9482239e4796a62326
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-on: http://openocd.zylin.com/2088
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Andrey Yurovsky <yurovsky@gmail.com>
fm3 flash driver needs to know which chip variant is used.
This fixes "unknown fm3 variant: mb9bf500.cpu" error if the config is
used as is.
Change-Id: I500fcfb413f23ee246678cec5bd19d14139a28e2
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2160
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This isn't needed nor a recommended practice now, was a simple
copy/paste from amdm37x.cfg anyhow.
Change-Id: I064226dc859d7563cfad945b577279fc37448645
Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-on: http://openocd.zylin.com/2068
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Maximum frequency wasn't tested on hardware but the docs seem to be
quite explicit and do not mention any restrictions for that.
Change-Id: Idcf58df5358d06525e683f07c76eedad8f0b292d
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2120
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This patch adds Micrel's KS869x target. The configuration was taken from
http://www.mmnt.net/db/0/0/www.micrel.com/ethernet/8695 - Micrel's
FTP server i.e. their OpenOCD 7.0 package.
The only change compared to the original file is the removal of
reset configuration, as it belongs to the board configuration.
Change-Id: Ic8509aa5fe5ce3166a3129e1c055280a3b2b9312
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-on: http://openocd.zylin.com/2125
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Old version of the code had several problems, among them are:
* Located in a generic ADI source file instead of some Kinetis
specific location
* Incorrect MCU detection code that would read generic ARM ID
registers
* Presence of SRST line was mandatory
* There didn't seem to be any place where after SRST line assertion
it would be de-asserted.
* Reset was asserted after waiting for "Flash Controller Ready" bit
to be set, which contradicts official programming guide AN4835
* Mass erase algorithm implemented by that code was very strange:
** After mass erase was initiated instead of just polling for the
state of "Mass Erase Acknowledged" bit the code would repeatedly
initiate mass erase AND poll the state of the "Mass Erase
Acknowledged"
** Instead of just polling for the state of "Flash Mass Erase in
Progress"(bit 0 in Control register) to wait for the end of the
mass erase operation the code would: write 0 to Control
register, read out Status register ignoring the result and then
read Control register again and see if it is zero.
* dap_syssec_kinetis_mdmap assumed that previously selected(before
it was called) AP was 0.
This commit moves all of the code to kinetis flash driver and
introduces three new commands:
o "kinetis mdm check_security" -- the intent of that function is to be used as
'examine-end' hook for any Kinetis target that has that kind of
JTAG/SWD security mechanism.
o "kinetis mdm mass_erase"" -- This function removes secure status from
MCU be performing special version of flash mass erase.
o "kinetis mdm test_securing" -- Function that allows to test securing
fucntionality. All it does is erase the page with flash security settings thus
making MCU 'secured'.
New version of the code implements the algorithms specified in AN4835
"Production Flash Programming Best Practices for Kinetis K-
and L-series MCUs", specifically sections 4.1.1 and 4.2.1.
It also adds KL26 MCU to the list of devices for which this security
check is performed. Implementing that algorithm also allowed to simplify
mass command in kinetis driver, since we no longer need to write security
bytes. The result that the old version of mass erase code can now be
acheived using 'kinetis mdm mass_erase'
Tested on accidentally locked FRDM-KL26Z with KL26 Kinetis MCU.
Change-Id: Ic085195edfd963dda9d3d4d8acd1e40cc366b16b
Signed-off-by: Andrey Smrinov <andrew.smirnov@gmail.com>
Reviewed-on: http://openocd.zylin.com/2034
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Add configuration file for General Plus GP326XXXA series. Tested on
GP326833A on GPC-1737B board.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Change-Id: I1ad0e22598b01317bbc823870a7a262e9192c595
Reviewed-on: http://openocd.zylin.com/2058
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The TI TMS470 and TMS570 series of processors are BE-32 processors,
despite BE-32 not being supported by ARM in the Cortex-R4 core. TI
hacked in BE-32 support, which requires odd swizzling in OpenOCD to
make memory reads and writes function correctly. In particular,
without this change, OpenOCD word reads and writes had the bytes
reversed, and halfword and byte packed reads were reading garbage.
In my testing, this change fixes these problems.
Change-Id: I21dd30f4b9003f20fcc85f674ab833407bb61f74
Signed-off-by: Seth LaForge <sethml@google.com>
Reviewed-on: http://openocd.zylin.com/2064
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Also add the board to the firmware recovery script.
Change-Id: I4f9c895dae171df7249e3b1c0563b288518b9fe0
Signed-off-by: Lee Bowyer <lee@sodnpoo.com>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2097
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
SoftDevice stack ihex binary, provided by Nordic expects being able to
write data necessary for its correct operation at the adresses inside UICR.
This patch exposes UICR region of flash as a second bank on the MCU to
facilitate that.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Change-Id: Idbc140b8de027f60655f78043877b7c054eb06f9
Reviewed-on: http://openocd.zylin.com/2013
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This adds support for the am43xx SoC and the AM437x GP EVM and AM438x
ePOS EVM.
Change-Id: I09cbb09072f38e0e08fdd520dedb6e67d45056be
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-on: http://openocd.zylin.com/2047
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
instead of replicating icepick_d_tapenable in many of TI's newer
platforms, we can move to icepick.cfg and just call it from board TCL
configuration file. This is similar to the C but has a few changes we
need to make.
Change-Id: I0ab48005ccd66cd5b67b919fb5e3b462288f211d
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-on: http://openocd.zylin.com/2030
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
From testing this target does not seem to support using SYSRESETREQ, change
the default to the safe VECTRESET.
This target also has other reset issues (srst not working) that will be
addressed in another patch.
Change-Id: Icfc78347dc71aa3a062ddea63190a818d7fbc760
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1995
Tested-by: jenkins
Reviewed-by: Angus Gratton <gus@projectgus.com>
Atmel's SAM3 and SAM4 processor families are very close to each other
in many respects. However, so far, only the SAM4 target script
contained the magic to allow using SWD, while SAM3 was tied to JTAG
only. This e.g. prevented the CMSIS-DAP driver from accessing SAM3
devices as it only uses SWD transport (by now).
The patch pulls all the things from the SAM4 target script that are
also applicable to SAM3 devices. With the patch, an Atmel CMSIS-DAP
debugger (Atmel-ICE) was proven to be able to successfully attach to a
SAM3S-EK evaluation kit. I also cross-checked that accessing through
a SAM-ICE (Segger J-Link) still works with the patch.
Change-Id: I20dafbff8e1e9f967da950e48a56205586eeef8d
Signed-off-by: Jörg Wunsch <openocd@uriah.heep.sax.de>
Reviewed-on: http://openocd.zylin.com/2046
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add support for Broadcom's dual A9 mobile SoC and its reference board.
Change-Id: Ia145b120043bddc89c44726066023154ae390788
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-on: http://openocd.zylin.com/1926
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
flash: at91sam4: add support for the SAMG53 family (this also covers the
SAMG51). The SAMG5x parts have an EEFC (enhanced embedded flash controller)
which seems to be identical to the EFC that the sam4 driver supports.
Add a script for the Xplained Pro G53 board, this has the onboard CMSIS-DAP
debugger and a SAMG53N19. Tested on this board and chip combination.
Change-Id: I12af50402cd2069b3c7380d92e6fe54816d6c045
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/1974
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Intel Quark X10xx SoC debug support added
Lakemont version 1 (LMT1) is the x86 core in Quark X10xx SoC
Generic x86 32-bit code is in x86_32_common.c/h
Change-Id: If2bf77275cd0277a82558cd9895b4c66155cf368
Signed-off-by: adrian.burns@intel.com
Reviewed-on: http://openocd.zylin.com/1829
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Originally the LPC17xx user guide (UM10360 Rev 2) stated that SYSRESETREQ
was not supported, so this was the default cortex_m reset mode.
Rev 3 of the same user guide states that it is now supported.
This has been verified on a LPC1768 mbed platform, previously I have not
tested this functionality.
Change-Id: I4858248903981a1c93ce75016e67c9e02702fcc5
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1892
Tested-by: jenkins
Reviewed-by: Jörg Fischer <turboj@gmx.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This adds a new NOR Flash driver, "at91samd", which supports the
built-in Flash on Atmel's D-series Cortex M MCUs, starting with the D20.
Parts and their geometry are detected automatically using the DSU and
lookup schemes described in the D20 document, 42129F–SAM–10/2013.
Future D-series variants and families should presumably use this
controller as well (possibly with minor changes and improvements).
Tested on the SAMD20 Xplained Pro board, for which we also add the
corresponding Flash configuration.
Change-Id: Id8d3dd601e9f53121682d1a1190d0be4ea3b83eb
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/1684
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This adds a new NOR Flash driver, "at91sam4l", which supports the
built-in Flash on Atmel's low-power SAM4L family of Cortex M4 MCUs.
Parts and their geometry are detected automatically using the Chip ID
and lookup schemes described in document 42023E–SAM–07/2013.
Tested on AT91SAM4LC4CA via the SAM4L XPlained Pro development kit.
Change-Id: If73499dee92cc8ce231845244ea25c6984f6cecd
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/1639
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
These kits feature a CMSIS-DAP compliant debugger and so have been added
as part of the pending support.
Currently the flash drivers for the L8 and D20 are wip.
One issue this implementation of CMSIS-DAP raised is that it supports
512byte HID reports, however using the current HIDAPI we have no cross platform
way of querying this info. Long term we plan to add this support to HIDAPI.
Change-Id: Ie8b7c871f58a099d963cd71a9f8a0105a38784e9
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1625
Tested-by: jenkins
This is based on work from:
https://github.com/TheShed/OpenOCD-CMSIS-DAP/tree/cmsis-dap
Main changes include moving over to using HIDAPI rather than libusb-1.0
and cleaning up to merge into master. Support for reset using srst has
also been added.
It has been tested on all the mbed boards as well as the Freedom board
from Freescale. These boards only implement SWD mode, however JTAG mode
has been tested with a Keil ULINK2 and a stm32 target - but requires a lot
more work.
Change-Id: I96d5ee1993bc9c0526219ab754c5aad3b55d812d
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/1542
Tested-by: jenkins
Tested flashing a real v1.1 device.
Change-Id: Ie0d202b9fded8b92e731d93e0ef17be415a75fc8
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1852
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This adds the bcm47xx config with the special undocumented trick to
put it into standard EJTAG mode from the mystic "LV mode".
The RAM setup is not done as it would require considerable efforts
without much practical gain.
The only issue I noticed so far is that "reset" doesn't actually reset
the chip.
Unfortunately, it's unclear how to make it work properly with SRST as
OpenOCD asserts it in MIPS-specific code so the device will enter LV
mode again but the LV tap is already disabled by that time, so it's
not possible to send the magic command again.
Anyway, this config is more than enough to "recover" any RT-N16
provided the hardware is not damaged.
Change-Id: I0894e339763e6d20d1c93341c597382b479d039b
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1849
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
* openocd.berlios.de -> openocd.sourceforge.net
* Update link to AM/DM37x Technical Reference Manual (ver R)
* "ICEpick" is properly spelled "ICEPick" according to TI
Change-Id: Ie04458e82c97ef766ec03bd9b9f27edadf5d1cb2
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Reviewed-on: http://openocd.zylin.com/1856
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The set command was missing the $ prefix on the SJC_TAPID variable
and so would fail if SJC_TAPID was set
Change-Id: Ib9af58f5188bd8a2bc3f888309f203d624476c27
Signed-off-by: Alex Murray <alex.murray@cohdawireless.com>
Reviewed-on: http://openocd.zylin.com/1811
Tested-by: jenkins
Reviewed-by: Jens Bauer <jens@gpio.dk>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Based on Nemuisan Tokusei's. Untested, but original config was reported
to work ok.
Change-Id: Ic991dce55bfca266880081fe2bbd9e6e263b0fc0
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1803
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
all other at91 cfg files already has this fix.
It also fix "No flash at address 0x...." error when JTAG chain consist of
more than one at91sam7sx cores during attempt to flash other than first mcu
in chain.
Change-Id: I7785d9103d0fc494b6a823e2c73f850373ffe112
Signed-off-by: Sergey A. Borshch <sb-sf@users.sourceforge.net>
Reviewed-on: http://openocd.zylin.com/1812
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
STM32F42xxx & STM32F43xxx series boudary scan TAP-ID are differ from
STM32F405xx/07xx & STM32F415xx/17xx.
And Section number was also fixed for RM0090 rev5.
Tested on a STM32F427IIT6 and STM32F429ZIT6.
Change-Id: Ie9c54c55b97b9c396ace752d94ea2ad916cc8479
Signed-off-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
Reviewed-on: http://openocd.zylin.com/1808
Tested-by: jenkins
Reviewed-by: Jens Bauer <jens@gpio.dk>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This is a Cortex-M1 controller targetting aviation appliances.
Contributed (and live-tested) by 8daemon.
Change-Id: I133d6122cf6492b51ddbdbd800c16ba121d51bf3
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1818
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This add support to the Xilinx BSCAN_* virtual JTAG interface.
This is the Xilinx equivalent of the Altera sld_virtual_jtag interface,
it allows a user to connect to the debug unit through the main
FPGA JTAG connection.
Change-Id: Ia438e910650cff9cbc8f810b719fc1d5de5a8188
Signed-off-by: Sergio Chico <sergio.chico@gmail.com>
Reviewed-on: http://openocd.zylin.com/1806
Tested-by: jenkins
Reviewed-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add support for the TMS570 Cortex-R4 MCU from TI and their USB stick
development kit, TMDX570LS31USB. Tested attaching, reset/halt/run, and
reading and writing memory and registers.
Change-Id: I12d779cef0c2b834f9bcf722307f35677cc4bd8f
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-on: http://openocd.zylin.com/1788
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Some boards might have RCLK omitted from the JTAG connector and if the
interface claims support for it, OpenOCD will end up trying to use
RCLK while it's actually impossible.
This is a "cd tcl/target; sed -i s/jtag_rclk/adapter_khz/g *" patch.
Change-Id: Iee7337107bc1457966b104389ba9db75a9c860b4
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1695
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Mathias Küster <kesmtp@freenet.de>
Initial support for using the jtag interface to the Marvell Armada 370
family of SoCs.
Change-Id: Id823a567e8805ac622c3c330bc111297c1dae37e
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Reviewed-on: http://openocd.zylin.com/1690
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add support for OpenRISC target. This implementation
supports the adv_debug_sys debug unit core. The mohor
dbg_if is not supported. Support for mohor TAP core
and Altera Virtual JTAG core are also provided.
Change-Id: I3b1cfab1bbb28e497c4fca6ed1bd3a4362609b72
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-on: http://openocd.zylin.com/1547
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The smallest available RAM size for this family is 2K, set this as the
default. Issue reported by quitte on IRC.
Change-Id: I3318f7f268f7681ffe2cddab61820f4b94c4e5fd
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1559
Tested-by: jenkins
This commit adds two tcl configuration files, one for the Altera
Cyclone V SoC series, and one for the SoCkit development board.
The board configuration is able to halt and resume the cpu cores,
and dump register contents etc. It has not been fully tested, however.
Change-Id: Id3f18c3408975cf986a5f5aec410b5b13240c35e
Signed-off-by: Brad Riensche <brad.riensche@gmail.com>
Reviewed-on: http://openocd.zylin.com/1494
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This adds example config and flash driver for russian Cortex-M3
microcontroller model.
Run-time tested on MDR32F9Q2I evaluation board; the flash driver
should be compatible with MDR32F2x (Cortex-M0) too but I lack hardware
to test.
There're no status bits at all, the datasheets specifies some delays
for flash operations instead. All being in <100us range, they're hard
to violate with JTAG, I hope. There're also no flash identification
registers so the flash size and type has to be hardcoded into the
config.
The flashing is considerably complicated because the flash is split
into pages, and each page consists of 4 interleaved non-consecutive
"sectors" (on MDR32F9 only, MDR32F2 is single-sectored), so the
fastest way is to latch the page and sector address and then write
only the part that should go into the current page and current sector.
Performance testing results with adapter_khz 1000 and the chip running
on its default HSI 8MHz oscillator:
When working area is specified, a target helper algorithm is used:
wrote 131072 bytes from file testfile.bin in 3.698427s (34.609 KiB/s)
This can theoretically be sped up by ~1.4 times if the helper
algorithm is fed some kind of "loader instructions stream" to allow
sector-by-sector writing.
Pure JTAG implementation (when target memory area is not available)
flashes all the 128k memory in 49.5s.
Flashing "info" memory region is also implemented, but due to the
overlapping memory addresses (resulting in incorrect memory map
calculations for GDB) it can't be used at the same time, so OpenOCD
needs to be started this way: -c "set IMEMORY true" -f
target/mdr32f9q2i.cfg
It also can't be read/verified because it's not memory-mapped anywhere
ever, and OpenOCD NOR framework doesn't really allow to provide a
custom handler that would be used when verifying.
Change-Id: I80c0632da686d49856fdbf9e05d908846dd44316
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1532
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Austriancoder on IRC reports getting this ID on his board.
Change-Id: Ie859f0ee422e18fdb94bf817cdd2b41d15b968da
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1533
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Pull the jtag_rtck setting from imx51.cfg and imx53.cfg . Since
not all boards using these CPUs do support RTCK signal, move the
configuration of RTCK into board files.
Change-Id: I632c5d38e00ada8779a451cd26428fd122452001
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/1460
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Ignore version of Boundary Scan TAP in newer revisions of the str9.
Change-Id: I6e205f8c731f07078c469e686025857c180f3a6d
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1436
Tested-by: jenkins
Add target code for Andes targets.
Change-Id: Ibf0e1b61b06127ca7d9ed502d98d7e2aeebbbe82
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1259
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Commit d9ba56c295 did a bunch of
renaming of cortex_a8 to cortex_a, including the names in config
files. However that introduced a regression as the name in target_type
struct remained unchanged.
This adds the last missing bit: actual renaming of the target name as
understood by OpenOCD.
Also change the (hopefully) last instance of using it in the supplied
config files, namely from imx6.cfg.
Change-Id: Ib9289fc6d946630133ec6e36c20015ccb50acf61
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1420
Tested-by: jenkins
Reviewed-by: Chris Johns <chrisj@rtems.org>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This is needed for configs that might be used with the cheapest
STM32F100 parts that have only 4kB SRAM.
Restrictions for the other STM32 families are verified to be set
appropriately.
Change-Id: I1ad2370435015604db9f27c1a76c153480311a28
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1378
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Due to reports of newer targets using a updated version of the ICEPick tap
rather than add another tapid we ignore the tap version.
Also see Trac 49 for details.
Change-Id: Ic78414c54af2545c817e1bb2c860970c1b587259
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1373
Tested-by: jenkins
Reviewed-by: Peter Stuge <peter@stuge.se>
Rename cortex_a8 target to use a more correct cortex_a name.
This also adds a deprecated_name var so that older scripts issue a warning
to update the target name.
cfg files have also been updated to the new target name.
Change-Id: I0eb1429c9281321efeb444b27a662a941a2ab67f
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1130
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Rename cortex_m3 target to use a more correct cortex_m name.
This also adds a deprecated_name var so that older scripts issue a warning
to update the target name.
cfg files have also been updated to the new target name.
Change-Id: Ia8429f38e88da677249c5caa560c50f8ce56ea10
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1129
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
As requested, here is the target configuration that I'm using for an
STLink-V2-attached STM32W108C8. For some reason, it only seems to work
with "reset_config trst_only".
Change-Id: Icbff4f83343e1f505d8afdfc53ff6f8b7496cac9
Signed-off-by: Ben Nahill <bnahill@gmail.com>
Reviewed-on: http://openocd.zylin.com/1347
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
By default pic32mx starts after any reset with 1 wait state for RAM access/exec.
It can be changed to 0 wait states by clearing the BMXWSDRM bit (bit 6) in BMXCON register.
With 0 wait states near doubles the execution speed. CRC check sum can be done much faster
increasing verify_image speed. Fast data transfer also works with a bit higher scan rate, up to 1500 Khz.
This option can be set at any time with
mww 0xbf882004 0x40
or cleared with
mww 0xbf882008 0x40.
Some numbers for FTDI/HS with current devel code and a elf file:
Core clock / wait states verify_image speed
------------------------------------|------------------------------
4 Mhz / 1 21 KiB/s
4 Mhz / 0 36 KiB/s
8 Mhz / 1 37 KiB/s
8 Mhz / 0 57 KiB/s
Change-Id: I4092ad0f3753f72f77108718d0ed3a3ab84e3b23
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1141
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Xiaofan <xiaofanc@gmail.com>
This change adds a simple target configuration for Freescale
single/dual/quad core i.MX6 SoCs, only one core is configured by default.
Change-Id: I853dd27f4c6765b7f731be2ddea82e85d496c6a4
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-on: http://openocd.zylin.com/1135
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch change the default reset config from SYSRESETREQ to the working
VECTRESET.
Change-Id: I21a9a74b9c0c68cfa3a6e6dac9b123acc98a93cb
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/1186
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This update adds support for the STM32Lx 384kb dual bank flash. Previously there was a problem when writing an
image that was larger than 192Kb. That lead to openocd printing out two error messages like
"Error: access denied / write protected" and "Error: invalid program address". The reason was that the stm32lx
driver tried to write half pages which overlapped into the next flash bank.
A new configuration file stm32lx_dual_bank.cfg can be used for stm32lx chips with dual bank flash (256kb or 384kb devices).
A sanity check was added for probed flash size values to fix the issue seen on some ST samples that answered incorrectly.
Change-Id: I69e25131983d88613be8606b438f98870c5f1e52
Signed-off-by: Johan Almquist <johan.almquist@assaabloy.com>
Reviewed-on: http://openocd.zylin.com/1125
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Limited (no page unprotect, no block writes) implementation of EFM32
flash support. Verified with EFM32 development kit and STLink V2 adapter
using SWD.
Change-Id: I3db2054d9aa628a1fe4814430425db3c9959c71c
Signed-off-by: Roman D <me@iamroman.org>
Reviewed-on: http://openocd.zylin.com/1106
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The smallest pert in the family has 10k RAM, so use that as a default
for the working area.
Change-Id: I78be0d14a254c109ac15a7163552c6132f810416
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1005
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Switch to using the internal HSI when a reset init is called, this also
matches the std stm32l cfg.
Read (verify) speed is increased from 17 to 120 KiB/s.
Change-Id: Ic94ba85949ffdefa17b7be45eef14e30f941d107
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1004
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This is the new proprietary interface replacing the older FTDI based adapters.
It is currently fitted to the ek-lm4f232 and Stellaris LaunchPad.
Change-Id: I794ad79e31ff61ec8e9f49530aca9308025c0b60
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/922
Tested-by: jenkins
As part of the switch to using the hla for the stlink interface we rename
the cmds to a more generic name.
Update scripts to match new names.
Also add handlers for deprecated names.
Change-Id: I6f00743da746e3aa13ce06acfdc93c8049545e07
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/921
Tested-by: jenkins
As for openocd 0.6.0-rc2 the function mips32_pracc_fastdata_xfer()
should now work at a scan frequency up to 1200Khz.
Mainly usefull to increase programming speed.
Also verify_image should be slightly faster.
Change-Id: I1e9b2be73690a4597e2f6ba069c1205026850f07
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/805
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Added a new configuration file for LPC18xx based boards, such as
HitexLPC1850RevA Evaluation Board, and all other based on the
same microcontroller by NXP.
Change-Id: I68c3827be535b6d09a5c70b6d57191937d00354d
Signed-off-by: Gianluca Renzi <gianlucarenzi@eurekelettronica.it>
Reviewed-on: http://openocd.zylin.com/930
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
If the target supports SYSRESETREQ make sure we use that as the default
if srst is not fitted/configured.
Change-Id: I24c907493134506320e69c1218702930629c1cdc
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/792
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Paul Fertser
Karl Palsson
Karl Palsson
Juha Niskanen
Uwe Bonnes
Spencer Oliver
Rémi PRUD'HOMME
Andreas Fritiofson
Vanya Sergeev
Бурага Александр
Angus Gratton
Andrey Skvortsov
Andrey Smirnov
Franck Jullien
Tom Rini
Yegor Yefremov
Seth LaForge
Lee Bowyer
Tim Sander
Felipe Balbi
Jörg Wunsch
Tim Kryger
Andrey Yurovsky
Fatih Aşıcı
Adrian Burns
Robert P. J. Day
Alex Murray
Sergey A. Borshch
Nemui Trinomius
Sergio Chico
Greg Ungerer
Brad Riensche
Marek Vasut
Giuseppe Barba
Hsiangkai Wang
Ben Nahill
Peter Dietzsch
Salvador Arroyo
Vladimir Zapolskiy
Mathias K
Johan Almquist
Roman D
is2t
Gianluca Renzi