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7968 Commits

Author SHA1 Message Date
Tim Newsome 603ed9c419
Merge pull request #167 from riscv/sifive_cfg 
Add config files for SiFive RISC-V hardware.
 2017-12-28 16:34:57 -08:00
Tim Newsome c27a777eb8
Merge pull request #165 from riscv/typo 
Fix typo.
 2017-12-28 16:13:11 -08:00
Tim Newsome 8150358cde Add config files for SiFive RISC-V hardware. 
Copied from https://github.com/gnu-mcu-eclipse/openocd

Change-Id: Ia0b3e192ca8b3bae6035623d605c9980e9bccd2c
 2017-12-28 16:10:41 -08:00
Tim Newsome 52368d6ea1 Fix typo. 
Issue #164

Change-Id: I083ba0d7df72a83a802297baa25753f8d274519a
 2017-12-28 11:52:59 -08:00
Tim Newsome 0774011e21
Merge pull request #163 from riscv/no_abort 
Get rid of abort() calls.
 2017-12-27 14:01:46 -08:00
Tim Newsome 365c79c3ff Get rid of abort() calls. 
Also changed a few asserts that could trigger due to broken hardware.

Fixes Issue #142.

Change-Id: Ia2b99baa82f30ebcb2fd7e4902f0e67046ce4ed2
 2017-12-27 13:45:50 -08:00
Tim Newsome d7ed191457
Merge pull request #162 from riscv/no_abort 
Propagate error instead of calling abort().
 2017-12-27 10:00:59 -08:00
Tim Newsome 06445f5743 Propagate error instead of calling abort(). 
As part of this I improved the memory read/write fatal error handling a
bit. Now at least we try to leave autoexec turned off, and will even
restore the temp registers if the situation isn't too hosed for that.

Partly addresses Issue #142

Change-Id: I79fe3f862f11c6d20441f39162423357e73a40c1
 2017-12-26 15:04:02 -08:00
Tim Newsome ca700dcef0
Merge pull request #161 from riscv/dead_code 
Remove unused code.
 2017-12-26 14:54:00 -08:00
Tim Newsome 4fa3d819d2 Remove unused code. 
Change-Id: Ibc72945ac76513c84d62616c0210e6013b21f7ef
 2017-12-26 14:27:44 -08:00
Tim Newsome 561b0c94c0
Merge pull request #160 from riscv/style 
Conform to OpenOCD style guide.
 2017-12-26 14:01:54 -08:00
Tim Newsome d942bce996 Conform to OpenOCD style guide. 
Change-Id: I2b23ac79639ed40e9d59db5c52ea2196df0349bc
 2017-12-26 11:38:11 -08:00
Tim Newsome 19d9e3e32a
Merge pull request #159 from riscv/update 
Merge changes from master
 2017-12-26 11:37:41 -08:00
Tim Newsome d2c92be73f Merge branch 'master' into update 
Change-Id: Icec244b174cc0c67ab58961649a369db7f344824
 2017-12-22 13:03:58 -08:00
Tim Newsome 6c719f0ab8
Merge pull request #156 from riscv/fespi 
fix fespi flash after registers were renamed.
 2017-12-22 12:00:11 -08:00
Tim Newsome 1f66c7827b Fix flash/run algorithm with new register names 
Change-Id: I8f539c880ee5da864956f56943411b228d8a5812
 2017-12-21 16:41:50 -08:00
Tim Newsome fadf2c1b48 Make functions static. Free memory. 
Change-Id: Iadf7b2a926d6d5abc4c8daa2f5620886bcb09b31
 2017-12-21 16:23:46 -08:00
Megan Wachs 33ef457c6a
Merge pull request #155 from riscv/debug_defines 
Update debug_defines to the one used with spike.
 2017-12-21 15:17:43 -08:00
Megan Wachs a81ad34af3
Merge pull request #148 from riscv/macbuild 
Use %ll instead of %L in scanf.
 2017-12-21 15:16:57 -08:00
Tim Newsome 5892b26259 Update debug_defines to the one used with spike. 
Change-Id: I627c6ee557d98239227324c33f9b89f6280cbf93
 2017-12-21 15:05:12 -08:00
Tim Newsome b01075eaa5
Merge pull request #145 from riscv/rbb_win 
Fix Windows build
 2017-12-21 14:04:33 -08:00
Tim Newsome 105536089b
Merge pull request #151 from riscv/use_paren 
Use parens after if.
 2017-12-21 12:50:56 -08:00
Tim Newsome fa385bdcd5 Use parens after if. 
I'm surprised this built with gcc before.

Fixes Issue #150.

Change-Id: I24d2957783c66ad53d5b532a4e930349a2059a97
 2017-12-21 12:43:22 -08:00
Jiri Kastner 1c2e3d41de config for ESPRESSObin from Globalscale Tech. Inc. 
Change-Id: I77f536a9d2e901ebcef0a7dd0f205e5332b1d382
Signed-off-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-on: http://openocd.zylin.com/4303
Tested-by: jenkins
Reviewed-by: Forest Crossman <cyrozap@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
 2017-12-20 19:47:11 +00:00
Jiri Kastner 84d68579eb configs for Marvell Armada 3700 
Change-Id: I367f39c9bc9e58380d6d5b500d5368d5173d96bd
Signed-off-by: Jiri Kastner <cz172638@gmail.com>
Signed-off-by: Forest Crossman <cyrozap@gmail.com>
Reviewed-on: http://openocd.zylin.com/4302
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
 2017-12-20 19:46:20 +00:00
Tim Newsome f13093fff7
Merge pull request #149 from riscv/xml_registers 
Send gdb an XML target description that contains only a list of registers we think exist on this target
 2017-12-19 11:13:19 -08:00
Tim Newsome 11c261cd50 Add `riscv expose_csrs` command. 
This lets users tell OpenOCD which non-standard CSRs exist on their
target, that will also be accessible and whose existence will be
communicated to gdb.

Change-Id: I56163a9fcb84ad7ebe815ae74fbd9fcc208f5a9d
 2017-12-19 10:41:48 -08:00
Tim Newsome 5f86f7208d Hide supervisor registers if there is no S mode. 
Also update encoding.h.

Change-Id: I275be7de0aa1af64d13ea191b9f4ff391cfb16dc
 2017-12-19 10:41:48 -08:00
Tim Newsome f55d1a2030 Give FPRs ABI names. 
Change-Id: If198d10e16671b9868836e23386aaf8d4b05f317
 2017-12-19 10:41:48 -08:00
Tim Newsome c7cddd2b5c Remove some debug printfs. 
Change-Id: I09989d4c0e102889ecb0eedbd3f4138f8b7bdb8c
 2017-12-19 10:41:48 -08:00
Tim Newsome 56ad0e5b30 Avoid another assertion failure. 
Change-Id: Ia54f778152974164697b712c360918e17a127d95
 2017-12-19 10:41:48 -08:00
Tim Newsome 10c17fdf17 Read misa before using it to check for extensions. 
Change-Id: I7a172d83055d8bd833e3349a5b22b47dd5f31f5c
 2017-12-19 10:41:48 -08:00
Tim Newsome ec1c814017 Don't rely on hart count until it's correct. 
Change-Id: I4e05eb091823b2e0fb481ca0b599072ba1ca70f2
 2017-12-19 10:41:48 -08:00
Tim Newsome 46715c7d8a Remove no-longer-true comment. 
Change-Id: I888680e73682582438a0de0496238867f1604754
 2017-12-19 10:41:48 -08:00
Tim Newsome 120477b2a2 Simplify examine() 
Now we don't have to play tricks fooling other parts of our code that
might assert.

Change-Id: Ia574378e1f95ed62d297e6b2e852245e58c9ffc9
 2017-12-19 10:41:48 -08:00
Tim Newsome 37278cf2ec Make priv register 8 bits. 
(It's really only 2 bits, but something wonky happens between gdb and
OpenOCD if I make it that size.)

Change-Id: I562a65cb0ebe5aa0edcc54c251d0fea0e26f9cb1
 2017-12-19 10:41:48 -08:00
Tim Newsome f341db9f72 WIP xml register for 0.11. 
On HiFive1, FPRs show up with no name, and misa is 0x1105 instead of
0x40001105.

Change-Id: I4ee223c905ad7d860147014e7b6394668658c6ea
 2017-12-19 10:41:48 -08:00
Tim Newsome 8926e66d3a Hide unknown registers, which probably don't exist 
Change-Id: Iffa8fa5ff4b0a01abd30fa302b7087e2011337bf
 2017-12-19 10:41:48 -08:00
Tim Newsome 26a54452d2 Fix register names. 
Use the ABI ones for every register that we have one for.

Change-Id: I2a993abff416d2652dbe026b3fb498e144a5006f
 2017-12-19 10:41:48 -08:00
Tim Newsome 7c989698a1 WIP better CSR names, and include only existing 
Change-Id: I1a234ee07c417ba56da10a61fc2bdbdcc60490a8
 2017-12-19 10:41:48 -08:00
Tim Newsome a5cb0b2270 WIP. Hide FPRs if the hart doesn't support F/D. 
Change-Id: I988c0c36f2de8157d76874a697b3c054773b787d
 2017-12-19 10:41:48 -08:00
Tim Newsome e648856a41 `make all` debug tests now pass. 
Also properly support (I think) D extension on RV32.

Change-Id: I2f0162d36e4c18c251f99b6943403cef30d17d29
 2017-12-19 10:41:48 -08:00
Tim Newsome c421fefdcb Checkpoint that seems to work. 
Change-Id: I9599aacc256f6340795097732b6f8e8869c2099f
 2017-12-19 10:41:48 -08:00
Tim Newsome 1e43d32e01 Use %ll instead of %L instead of scanf. 
Mac build barfs on L, and the manpage says they're equivalent.

Hopefully fixes #147

Change-Id: I3aa57775731f3f5ceb03097cae2a9dc6fd426dcd
 2017-12-15 15:31:36 -08:00
Tim Newsome b8db82fb57
Merge pull request #146 from riscv/scratch_ram 
Fix cut and paste bug.
 2017-12-14 14:22:10 -08:00
Tim Newsome 6aff46adcc Fix cut and paste bug. 
Now reading 64-bit FPRs on 32-bit harts using scratch memory might work.

Change-Id: Ie8c0fc689386c6e724ecab5e8c855e725fa8dd97
 2017-12-14 13:51:13 -08:00
Tim Newsome 7eceac758c Use abstraction because Windows is not POSIX 
Fixes #138

Change-Id: I4d9b49762e318fe91f1561ed315829b43daefef4
 2017-12-14 12:36:42 -08:00
Tim Newsome 3624d5e5eb Add win32 build to travis. 
Change-Id: I8ce62ff321c6f3627d42fff13236f7fc9440d429
 2017-12-14 12:36:21 -08:00
Tomas Vanek 19f8f58c0d target: remove unused event definitions 
Events reset-halt-pre, reset-halt-post, reset-wait-pre and
reset-wait-post are not used anywhere.

Change-Id: I9a0f94875b102d9b08f6c2fd9d73a9f05f8e8e79
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4285
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
 2017-12-12 21:18:10 +00:00
Tomas Vanek 3f6ab8e6a6 flash/nor/stm32f2x: fix erase on STM32F413/423 
Theese devices do not have a gap in sector numbering.
The driver translates sectors numbers 12 13... to 16 17... as used on dual
bank flash devices. Therefore erase of sector 12 and above fails with error
	'stm32x device protected'
on F413/423.

Drop sector number translation for devices without has_large_mem flag.

Change-Id: I65531c0dfe02e2fd0f3d68f0615e0926e9901391
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4299
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
 2017-12-12 21:16:24 +00:00