Check that the value of dtmcs.abits is in the expected range.
Make corrections of data types in batch.{c,h} and in related code.
Some of the issues were found by activating "-Wconversion" in GCC,
others by inspecting the code manually.
This is an initial step towards being able to use "-Wconversion" on
RISC-V target code, which will give us bit more confidence when
refactoring or merging new patches.
Changes made:
- Check `dtmcs.abits` during examination.
- DMI address is no larger than 32-bits per the debug spec.
Changed address parameters of multiple functions from uint64_t
to uint32_t.
- The value passed to jtag_add_runtest() is now `unsigned int`,
not `int`. No need for `assert(idle <= INT_MAX)` anymore.
- `get_delay()` in batch.c can return an unsigned value.
- Added few assertions around `field->num_bits` in batch.c.
Change-Id: Ibfccd62d552063df6ab9b5a2d4ea4ed23617d3db
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
* Registers were not invalidated if the hart became unavailable.
* Improved logging in the case register invalidation involves loss of
information.
Change-Id: Icfb5e190dd6dcb1a97e4d314d802466cab7a01e4
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
This changes will allow to unite read_memory/write_memory fucntions
to one access function
(1) Replaced read/write functions arguments with one structure
(2) Unified read_memory/write_memory function pointers
to be stored in same structure
Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
this commit fixes a regression introduced in
ba8c1eef5a.
The regression was caused by removal of these lines:
```
- /* Register prefix: "csr_" or "custom_" */
- strcpy(name, reg_type);
- name[strlen(reg_type)] = '_';
```
causing all CSR names with custom names to be parsed as empty strings.
Two cases where single step is needed before resume:
1. ebreak used in software breakpoint;
2. a trigger that is taken just before the instruction
that triggered it is retired.
Signed-off-by: Songhe Zhu <zhusonghe@eswincomputing.com> Co-developed-by: Fei Gao <gaofei@eswincomputing.com> Co-developed-by: xiatianyi <xiatianyi@eswincomputing.com>
Per current OpenOCD conventions, LOG_ERROR should not be printed
when ERROR_COMMAND_SYNTAX_ERROR is returned. OpenOCD will print
the command syntax to the user on its own.
Existing flags: 'enable_virtual' and 'enable_virt2phys' were
replaced with explicit translation drivers. Motivation:
(1) Having 'enable_virtual' and 'enable_virt2phys' flags set simultaneously
may cause double address translation which is unacceptable
(2) Flags were global for all targets which is wrong too
Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
Conversion done with
checkpatch --fix-inplace -types UNSPECIFIED_INT
Ignore the cast as they could be better addressed.
Fix only minor additional checkpatch issue (spacing and line
length).
Change-Id: I11f10eddadc21e051c96eb3d4d4c0554a2cddd15
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8483
Tested-by: jenkins
(1) Error code and 'skip_reason' string were replaced with memory access
status. It allows to specify whether OpenOCD should exit the access
early.
(2) Slightly refactored 'read_memory' and 'write_memory' functions.
Checkpatch-ignore: MACRO_ARG_PRECEDENCE, MULTISTATEMENT_MACRO_USE_DO_WHILE
Checkpatch-ignore: TRAILING_SEMICOLON
Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
Before the change, if the user wrote to any `tdata*` register, OpenOCD
would sometimes start to disable all the triggers (by writing zeroes to
`tdata1`) and re-enable them again (by witing all trigger registers to the
values read before for each `tselect` value), e.g. on `step`
(see `disable/enable_triggers()`).
There are a couple of issues with such approach:
1. RISC-V Debug Specification does not require custom register types
to support re-enabling by such sequence of writes (e.g. some custom
trigger type may require writing a custom CSR to enable it).
2. OpenOCD may still overwrite these triggers when a user asks to set a
new WP.
This commit introduces `riscv reserve_trigger ...` command to explicitly
mark the triggers OpenOCD should not touch.
Such approach allows to separate management of custom triggers and
offload it onto the user (e.g. disable/enable such triggers by setting up
an event handler on `step`-related events).
Change-Id: I3339000445185ab221368442a070f412bf44bfab
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
* removed `progbuf_size` field from `riscv_info`; added getter
* moved `impebreak` field from `riscv_info` to `riscv013_info`
as implementation dependent field; added getter
Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
Logically, BSCAN tunneling is used to establish a connection, therefore
it should be set up before the communication starts (i.e. before
`init`).
Moreover, current implementation does not support changing
`bscan_tunnel_ir_width` after `init`. This is evident by RISC-V handler
of the `init` itself.
Link: 9a23c9e679/src/target/riscv/riscv.c (L467-L481)
Change-Id: I817c6a996f7f7171b2286e181daf1092bd358f69
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Also avoid receiving data if the value is discarded on the call-site.
Change-Id: Ied87b551536a00d9fad469b9843cccae1976e6b6
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
* Eliminates the use of VLA, which is prohibited by `doc/manual
/style.txt`:
Link: c6bb902629/doc/manual/style.txt (L164-L166)
* Unifies DMI access interface.
* Reduces code duplication.
Change-Id: I2d7b0595f171e21062049ff61f76fb5a3c992d11
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
This commit creates file structure for register cache related
functions.
Specifically:
* `riscv_reg.h` -- general interface to registers. Safe to use after
register cache initialization is successful.
* `riscv_reg_impl.h` -- helper functions to use while implementing
register cache initialization.
* `riscv_reg.c` -- definitions of functions from `riscv_reg.h` and
`riscv_reg_impl.h`.
* `riscv-011_reg.h` -- register cache interface specific to 0.11
targets.
* `riscv-013_reg.h` -- register cache interface specific to 0.13+
targets.
* `riscv-011/0.13.h` -- version-specific methods used to access
registers. Will be extended as needed once other functionality (not
related to register access) is separated (e.g. DM/DTM specific stuff).
Change-Id: I7918f78d0d79b97188c5703efd0296660e529f2a
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
this functionality allows to query if a target belongs to some smp group
and to dynamically turn on/off smp-specific behavior
Change-Id: I67bafb1817c621a38ae4a2f55e12e4143e992c4e
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8296
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Caching is somewhat handled in `riscv-011.c`. Handling it additionaly in
`riscv.c` may cause problems. Sice there is no simulator that supports
RISC-V Debug Specification v0.11, so it is not feaseable to automate
testing.
This commit separates 0.11 register accesses and unlocks further
development in this area.
Change-Id: I73ff17ef85106c4ababa38319f446f6c384a1750
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
hide_csrs should not emit warnings on an attempt to hide non-exitents CSR.
hide_csrs funcitonality is intended to be used for scenarios when we don`t
want certain groups of registers to be available in GDB. Typically this is
needed to simplify integration with various IDE. In such scenarious it may
be impractical/unfeseable to figure out which register is present on a
target. So reporting a situation when a user wants to hide a non-existent
register creates way too much noise. This commit reduces severity of
relevant debug message to LOG_TARGET_DEBUG
Before this patch the following behavior is observed on targets that do
not support hit bit:
```
bp 0x80000004 4 hw
resume 0x80000000
riscv.cpu halted due to watchpoint
```
This happens because the current implementation relies on the presence
of hit bit way too much. While working on this patch few defects in
hit bit-based trigger detection were discovered, added appropriate
TODOs.
For GDB to fully support hardware watchpoints, OpenOCD needs to tell GDB
which data address has been hit. OpenOCD relies on a target-specific
hit_watchpoint function to do this. If GDB is not given the address, it
will not print the hit variable name or its old and new value.
There does not seem to be a way for the hardware to tell us which
trigger
was hit (0.13 introduced the 'hit bit' but this is optional).
Alternatively,
we can decode the instruction at dpc and find out which memory address
it accesses.
This commit adds support for RVC (compressed) load and store
instructions.
Related to:
https://github.com/riscv-collab/riscv-openocd/issues/688https://github.com/riscv-collab/riscv-openocd/pull/291
This commit is related to testing how OpenOCD responds to `dmi.busy`.
Consider testing on Spike (e.g. `riscv-tests/debug` testsuite). Spike
returns `dmi.busy` if there were less then a given number of RTI cycles
(`required_rti_cycles`) between DR_UPDATE and DR_CAPTURE:
https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/jtag_dtm.cc#L145https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/jtag_dtm.cc#L202
`required_rti_cycles` gets it's value from `--dmi-rti` CLI argument and
is constant throughout the run.
OpenOCD learns this required number of RTI cycles by starting with zero
and increasing it if `dmi.busy` is encountered. So the required number
of RTI cycles is learned during the first DMI access in the `examine()`.
To induce `dmi.busy` on demand `riscv reset_delays <x>` command is
provided. This command initializes `riscv_info::reset_delays_wait`
counter to the provided `<x>` value. The counter is decreased before a
DMI access and when it reaches zero the learned value of RTI cycles
required is reset, so the DMI access results in `dmi.busy`.
Now consider running a batch of accesses. Before the change all the
accesses in the batch had the same number of RIT cycles in between them.
So either:
* Number of accesses in the batch was greater then the value of
`riscv_info::reset_delays_wait` counter and there was no `dmi.busy`
throughout the batch.
* Number of accesses in the batch was less or equal then the value of
`riscv_info::reset_delays_wait` counter and the first access of the
batch resulted in `dmi.busy`.
Therefore it was impossible to encounter `dmi.busy` on any scan of the
batch except the first one.
Change-Id: Ib0714ecaf7d2e11878140d16d9aa6152ff20f1e9
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Evgeniy Naydanov
Evgeniy Naydanov
Jan Matyas
Anatoly Parshintsev
Farid Khaydari
Parshintsev Anatoly
zhusonghe
Mark Zhuang
Antonio Borneo
Tim Newsome
Aleksey Lotosh