4af702c9c4
stw
2017-04-14 19:55:32 -07:00
763e5cb44c
memoize
2017-04-14 17:44:47 -07:00
6c74c1c6f3
runs hart0
2017-04-14 17:25:50 -07:00
79fb51fe7b
read byte
2017-04-14 16:23:29 -07:00
9a04773c75
endian
2017-04-14 16:23:16 -07:00
62659905ca
regaddr
2017-04-14 16:22:56 -07:00
02012f2604
fence.i
2017-04-14 14:34:01 -07:00
747f769f7d
unhalt
2017-04-14 14:19:40 -07:00
57d08889ce
later
2017-04-14 14:17:27 -07:00
d652e6ea16
off by one
2017-04-13 22:11:07 -07:00
22d102e3c1
Fix a buffer overflow
2017-04-13 18:52:11 -07:00
98df29b8d1
Check for step
2017-04-13 17:22:59 -07:00
e481524362
Replace the 0.13-specific "program_t" with a generic one
...
This new version changes how we handle temporary registers: rather than
tracking them by hand (like in the old code), they're now tracked as
part of assembling programs. The register save/restore assertion that
used to fire all the time no longer exists.
2017-04-13 14:37:20 -07:00
0e54044ac7
Remove Off By 1 FIXME because HW is fixed
2017-04-10 14:24:02 -07:00
3c5cb81a09
Implement the "vCont" GDB packet
2017-04-07 18:32:54 -07:00
ad157ec0f6
typo in comment
2017-04-07 15:43:23 -07:00
a4d3a8d415
Determine the trigger count dynamically
2017-04-07 15:26:24 -07:00
dd4677c3df
Determine the hart count dynamically
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This assumes that v0.11 targets have one hart, and that v0.13 targets
have harts IDs that start at 0 and are concecutive.
2017-04-07 15:26:17 -07:00
74095335dc
Call riscv_xlen() to support 32-bit FESPI targets
2017-04-06 15:23:45 -07:00
d0fcbc9b51
Add a RISC-V RTOS, which natievly supports multiple harts
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This is a work in progress, but it's at the point where you can actually
debug multi-hart programs now.
2017-04-06 15:23:40 -07:00
7203102c25
Merge pull request #28 from sifive/readmem_autoexec
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Readmem autoexec
2017-04-04 22:27:52 -07:00
14e26040b8
riscv: move value read to after autoexec is cleared.
2017-04-04 16:33:17 -07:00
9c1f6ea28b
riscv: Correct the autoexec in read_mem
2017-04-04 16:22:55 -07:00
69a8273da5
Merge pull request #23 from sifive/w1-to-clear-cmderr
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riscv: Use write-1-to-clear for CMDERR, not write 0 to clear.
2017-03-30 15:10:56 -07:00
eb90a5e05e
riscv: Use write-1-to-clear for CMDERR, not write 0 to clear.
2017-03-30 14:27:28 -07:00
7df6804934
Revert "(WIP) Force algorithms to 64 bit"
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This reverts commit 466b7b4881
2017-03-23 19:46:54 -07:00
466b7b4881
(WIP) Force algorithms to 64 bit
2017-03-23 19:21:02 -07:00
ae51b92480
some device
2017-03-23 14:51:30 -07:00
03fa9d22c4
Don't set abstractauto at the start
2017-03-23 14:50:40 -07:00
84fa7aa916
Merge pull request #21 from sifive/read_memory_retry
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Read memory retry
2017-03-22 18:00:44 -07:00
a7499161e0
Merge remote-tracking branch 'origin/riscv' into read_memory_retry
2017-03-22 17:53:23 -07:00
c61b3efe9a
riscv: Retry failed memory reads
2017-03-22 17:51:46 -07:00
5f9cc2ce5f
Turn off autoexec after read_memory()
2017-03-22 14:28:39 -07:00
98420e377a
riscv: add missing variable declaration.
2017-03-21 23:47:21 -07:00
09da0c812f
Clear autoexec correctly
2017-03-21 17:20:11 -07:00
6033850415
Wrong autoexec
2017-03-21 17:20:11 -07:00
0c790d385d
Builds
2017-03-21 17:20:11 -07:00
c09ccbcc7c
Merge pull request #20 from sifive/delay_after_autoexec
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riscv-v13: wait for idle in read_memory
2017-03-21 13:18:26 -07:00
a70e628620
riscv-v13: wait for idle in read_memory
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read_memory was doing autoexec-initialized commands, but wasn't using
ac_busy_delay to add delay or wait between the commands. This isn't the optimal
solution, but the whole read_memory sequence needs to be made more efficient
anyway, so this was the quick and dirty solution.
2017-03-15 17:23:21 -07:00
bb39d3b17e
Remove more cruft.
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Change-Id: I24d545cc259927301851fad446f812e95fd1c557
2017-02-27 20:27:07 -08:00
8785b256cb
Merge pull request #18 from sifive/halt_correctly
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riscv: Ensure that hart is halted before attempting to examine it.
2017-02-27 20:17:42 -08:00
7f13e90505
riscv: Ensure that hart is halted before attempting to examine it.
2017-02-27 18:53:50 -08:00
b4d38d0997
Remove cruft.
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Change-Id: I3a370aa3a478ab84c9b2afff7b3f581bd7dc5e06
2017-02-25 10:40:56 -08:00
6f1a498ab9
Use DCSR constants from the debug spec.
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Replace the constants with the ones from the ISA spec, since those are
not updated as often.
Also delete a bunch of old code.
Change-Id: I9201b1455d64a9d2d203bb362fefaa68cbf35aeb
2017-02-25 10:34:46 -08:00
8f6ddc92e8
Update bits to latest spec.
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Change-Id: Ib09e1da81c6c0e7c9c6b69e9fe31eda20e3cd6e0
2017-02-25 10:17:27 -08:00
3bd661b679
Speed things up by ignoring return values.
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The remote bitbang implementation is really slow when reading back data.
During many operations, like writing a block of memory, we don't need to
see the return data. By communicating this to the lower layers, we get
huge speedups. Downloads to spike now are 295KB/s.
That means the gdbserver.py download test now runs to completion,
unfortunately it fails. Everything else is still passing, though, so I'm
committing this change.
Change-Id: I44cc9db1ade0908c1a12d09b23fc8e529a802d88
2017-02-22 16:04:36 -08:00
f9168b09d0
Optimize memory write code, used in download.
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To spike now we download at 5KB/s. But in real hardware performance
should be pretty OK now.
Change-Id: Ie6086cf156c9a00ac55400870346e27b28e3c755
2017-02-21 20:31:50 -08:00
4e8cf4aeb5
Better error checking in memory access.
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Change-Id: I985afa433a09f833137f2e244b7eaad2630f6b1a
2017-02-20 17:53:18 -08:00
aba0c0973d
Properly restore s0 and s1 on resume.
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Now 33/39 of the gdbserver tests pass!
Change-Id: I0cb38fbbcdc2c037ff0ec77229e79f24fa021663
2017-02-20 15:47:31 -08:00
3173314f28
Fix access FPU registers again.
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Not a great fix. There's still a problem with accessing 64-bit floating
point registers on 32-bit cores.
24 of the gdbserver.py tests pass now.
Change-Id: I69a88ef5fd5581e2c7bf1d78057fd474ae86ff93
2017-02-17 19:03:32 -08:00
Palmer Dabbelt
mwachs5
Tim Newsome