Determine the trigger count dynamically
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@ -139,8 +139,6 @@ typedef struct {
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// unique_id of the breakpoint/watchpoint that is using it.
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int trigger_unique_id[MAX_HWBPS];
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unsigned int trigger_count;
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// Number of run-test/idle cycles the target requests we do after each dbus
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// access.
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unsigned int dtmcontrol_idle;
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@ -929,11 +927,12 @@ static void deinit_target(struct target *target)
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static int add_trigger(struct target *target, struct trigger *trigger)
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{
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riscv013_info_t *info = get_info(target);
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RISCV_INFO(r);
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maybe_read_tselect(target);
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unsigned int i;
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for (i = 0; i < info->trigger_count; i++) {
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for (i = 0; i < riscv_count_triggers(target); i++) {
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if (info->trigger_unique_id[i] != -1) {
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continue;
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}
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@ -994,7 +993,7 @@ static int add_trigger(struct target *target, struct trigger *trigger)
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info->trigger_unique_id[i] = trigger->unique_id;
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break;
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}
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if (i >= info->trigger_count) {
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if (i >= riscv_count_triggers(target)) {
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LOG_ERROR("Couldn't find an available hardware trigger.");
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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@ -1009,12 +1008,12 @@ static int remove_trigger(struct target *target, struct trigger *trigger)
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maybe_read_tselect(target);
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unsigned int i;
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for (i = 0; i < info->trigger_count; i++) {
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for (i = 0; i < riscv_count_triggers(target); i++) {
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if (info->trigger_unique_id[i] == trigger->unique_id) {
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break;
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}
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}
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if (i >= info->trigger_count) {
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if (i >= riscv_count_triggers(target)) {
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LOG_ERROR("Couldn't find the hardware resources used by hardware "
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"trigger.");
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return ERROR_FAIL;
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@ -1239,7 +1238,6 @@ static int examine(struct target *target)
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/* Examines every hart, first checking XLEN. */
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for (int i = 0; i < riscv_count_harts(target); ++i) {
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RISCV_INFO(r);
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riscv_set_current_hartid(target, i);
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if (abstract_read_register(target, NULL, S0, 128) == ERROR_OK) {
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@ -1254,8 +1252,19 @@ static int examine(struct target *target)
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}
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}
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/* FIXME: Are there 2 triggers? */
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info->trigger_count = 2;
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/* Then we check the number of triggers availiable to each hart. */
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for (int i = 0; i < riscv_count_harts(target); ++i) {
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for (int t = 0; t < RISCV_MAX_TRIGGERS; ++t) {
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riscv_set_current_hartid(target, i);
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r->trigger_count[i] = t;
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register_write_direct(target, GDB_REGNO_TSELECT, t);
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uint64_t tselect = t+1;
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register_read_direct(target, &tselect, GDB_REGNO_TSELECT);
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if (tselect != t)
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break;
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}
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}
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/* Resumes all the harts, so the debugger can later pause them. */
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riscv_resume_all_harts(target);
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@ -1008,3 +1008,15 @@ enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid)
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assert(riscv_is_halted(target));
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return r->halt_reason(target);
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}
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int riscv_count_triggers(struct target *target)
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{
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return riscv_count_triggers_of_hart(target, riscv_current_hartid(target));
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}
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int riscv_count_triggers_of_hart(struct target *target, int hartid)
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{
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RISCV_INFO(r);
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assert(hartid < riscv_count_harts(target));
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return r->trigger_count[hartid];
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}
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@ -7,6 +7,7 @@
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/* The register cache is staticly allocated. */
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#define RISCV_MAX_HARTS 32
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#define RISCV_MAX_REGISTERS 5000
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#define RISCV_MAX_TRIGGERS 32
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extern struct target_type riscv011_target;
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extern struct target_type riscv013_target;
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@ -64,6 +65,9 @@ typedef struct {
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/* The state of every hart. */
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enum riscv_hart_state hart_state[RISCV_MAX_HARTS];
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/* The number of triggers per hart. */
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int trigger_count[RISCV_MAX_HARTS];
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/* Helper functions that target the various RISC-V debug spec
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* implementations. */
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riscv_reg_t (*get_register)(struct target *, int, int);
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@ -177,4 +181,9 @@ bool riscv_is_halted(struct target *target);
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bool riscv_was_halted(struct target *target);
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enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid);
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/* Returns the number of triggers availiable to either the current hart or to
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* the given hart. */
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int riscv_count_triggers(struct target *target);
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int riscv_count_triggers_of_hart(struct target *target, int hartid);
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#endif
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