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313 Commits

Author SHA1 Message Date
Gleb Gagarin 5c543ee3a1 complete reset before writing to hartsel field 2018-02-07 16:06:02 -08:00
Tim Newsome 6f0d70f5c8 Mention register name instead of number in error 
Change-Id: I5be5e57418e672fc76383fc24635cdbfb1e65578
 2018-01-30 12:30:39 -08:00
Tim Newsome 6a98fb7076 Detect hartsellen, limiting which harts we probe 
Tested with doctored spike with hartsellens of 0, 1, 3, and 10.

Change-Id: I97f57c7d03b076792d5ecd66545d9b9e853ed515
 2018-01-26 16:39:58 -08:00
Tim Newsome 2d263bae84 Make all memory logging lines consistent. 
Also reduce a few 64-bit variables to 32 bits, which is all they need.

Change-Id: I23e431b7eed4a63803add93a1bb328a3631631d6
 2018-01-24 13:53:11 -08:00
Tim Newsome 42e601afc1
Merge pull request #191 from riscv/scanbuild 
Fix some niggles found by clang's static analysis.
 2018-01-24 07:59:47 -08:00
Tim Newsome 553a63808c Fix some niggles found by clang's static analysis. 
Change-Id: Id476227e1bd02e067f0cc4da9bc7ffb3d9d30535
 2018-01-23 15:16:23 -08:00
Tim Newsome 3839cbf0ad Add some error checking to examine(). 
Fixes #183.

Change-Id: I6fb45adf4c97ea339c9d4ca3b372a09b18e3b56e
 2018-01-19 13:58:02 -08:00
Tim Newsome 7f368468c8 Remove dead code. 
Change-Id: Ic90598b3dd4128dabb18ac4dc1285ca721a6a441
 2018-01-15 12:07:20 -08:00
Megan Wachs 6f9585068f
Merge pull request #172 from riscv/dbus_read_comment 
Add a comment in dbus_read
 2018-01-10 15:30:56 -08:00
Tim Newsome 0d60a29c21
Merge pull request #178 from riscv/cleanup 
Rename dummy variable to be correct.
 2018-01-10 15:16:40 -08:00
Tim Newsome 29c7a76708 Muck with mstatus to always be able to read FPRs 
Change-Id: I7ff8bde4578c9ddd175c5cca370295c790cfbba7
 2018-01-09 12:06:11 -08:00
Tim Newsome fd506fa839 Propagate register read errors. 
Change-Id: Idda111377873a2236b5b91e4ffdabd2be384b47a
 2018-01-08 11:53:02 -08:00
Tim Newsome 0e3869cbf6
Merge pull request #179 from riscv/multicore_hart_selection 
Select current hart before reading memory.
 2018-01-05 14:07:38 -08:00
Tim Newsome 11e51af3b1
Merge pull request #173 from riscv/warn_names 
Use register names instead of numbers in warnings
 2018-01-05 13:07:08 -08:00
Tim Newsome 37434ffd77 Rename dummy variable to be correct. 
Change-Id: I329404894227bb3cf563382e1adf0edda702543b
 2018-01-05 13:05:33 -08:00
Tim Newsome 6f3913cedc Select current hart before reading memory. 
This avoids trying to read memory from the wrong hart, if the current
hart was changed by an earlier call (eg. to poll()).

Change-Id: I73da1e01c8d01d68f01ac7fdd6c548380a70cfd3
 2018-01-04 17:12:01 -08:00
Tim Newsome 097d62d159 Make delay update messages debug instead of info. 
They confuse users otherwise.

Change-Id: I3bc491352f5384e36c54696a0ecbf11ac623dd83
 2018-01-04 13:36:53 -08:00
Megan Wachs 33aad3524b
Add a comment in dbus_read 
This just comments the current behavior
 2018-01-04 13:27:35 -08:00
Tim Newsome 07e19e17cb Use register names instead of numbers in warnings 
Change-Id: Ie2295d30fd9dfeb7590f5e34d572497a93a3ce7b
 2018-01-04 13:27:18 -08:00
Tim Newsome 365c79c3ff Get rid of abort() calls. 
Also changed a few asserts that could trigger due to broken hardware.

Fixes Issue #142.

Change-Id: Ia2b99baa82f30ebcb2fd7e4902f0e67046ce4ed2
 2017-12-27 13:45:50 -08:00
Tim Newsome 06445f5743 Propagate error instead of calling abort(). 
As part of this I improved the memory read/write fatal error handling a
bit. Now at least we try to leave autoexec turned off, and will even
restore the temp registers if the situation isn't too hosed for that.

Partly addresses Issue #142

Change-Id: I79fe3f862f11c6d20441f39162423357e73a40c1
 2017-12-26 15:04:02 -08:00
Tim Newsome 4fa3d819d2 Remove unused code. 
Change-Id: Ibc72945ac76513c84d62616c0210e6013b21f7ef
 2017-12-26 14:27:44 -08:00
Tim Newsome d942bce996 Conform to OpenOCD style guide. 
Change-Id: I2b23ac79639ed40e9d59db5c52ea2196df0349bc
 2017-12-26 11:38:11 -08:00
Tim Newsome 1f66c7827b Fix flash/run algorithm with new register names 
Change-Id: I8f539c880ee5da864956f56943411b228d8a5812
 2017-12-21 16:41:50 -08:00
Megan Wachs 33ef457c6a
Merge pull request #155 from riscv/debug_defines 
Update debug_defines to the one used with spike.
 2017-12-21 15:17:43 -08:00
Megan Wachs a81ad34af3
Merge pull request #148 from riscv/macbuild 
Use %ll instead of %L in scanf.
 2017-12-21 15:16:57 -08:00
Tim Newsome 5892b26259 Update debug_defines to the one used with spike. 
Change-Id: I627c6ee557d98239227324c33f9b89f6280cbf93
 2017-12-21 15:05:12 -08:00
Tim Newsome fa385bdcd5 Use parens after if. 
I'm surprised this built with gcc before.

Fixes Issue #150.

Change-Id: I24d2957783c66ad53d5b532a4e930349a2059a97
 2017-12-21 12:43:22 -08:00
Tim Newsome 11c261cd50 Add `riscv expose_csrs` command. 
This lets users tell OpenOCD which non-standard CSRs exist on their
target, that will also be accessible and whose existence will be
communicated to gdb.

Change-Id: I56163a9fcb84ad7ebe815ae74fbd9fcc208f5a9d
 2017-12-19 10:41:48 -08:00
Tim Newsome 5f86f7208d Hide supervisor registers if there is no S mode. 
Also update encoding.h.

Change-Id: I275be7de0aa1af64d13ea191b9f4ff391cfb16dc
 2017-12-19 10:41:48 -08:00
Tim Newsome f55d1a2030 Give FPRs ABI names. 
Change-Id: If198d10e16671b9868836e23386aaf8d4b05f317
 2017-12-19 10:41:48 -08:00
Tim Newsome c7cddd2b5c Remove some debug printfs. 
Change-Id: I09989d4c0e102889ecb0eedbd3f4138f8b7bdb8c
 2017-12-19 10:41:48 -08:00
Tim Newsome 56ad0e5b30 Avoid another assertion failure. 
Change-Id: Ia54f778152974164697b712c360918e17a127d95
 2017-12-19 10:41:48 -08:00
Tim Newsome 10c17fdf17 Read misa before using it to check for extensions. 
Change-Id: I7a172d83055d8bd833e3349a5b22b47dd5f31f5c
 2017-12-19 10:41:48 -08:00
Tim Newsome ec1c814017 Don't rely on hart count until it's correct. 
Change-Id: I4e05eb091823b2e0fb481ca0b599072ba1ca70f2
 2017-12-19 10:41:48 -08:00
Tim Newsome 46715c7d8a Remove no-longer-true comment. 
Change-Id: I888680e73682582438a0de0496238867f1604754
 2017-12-19 10:41:48 -08:00
Tim Newsome 120477b2a2 Simplify examine() 
Now we don't have to play tricks fooling other parts of our code that
might assert.

Change-Id: Ia574378e1f95ed62d297e6b2e852245e58c9ffc9
 2017-12-19 10:41:48 -08:00
Tim Newsome 37278cf2ec Make priv register 8 bits. 
(It's really only 2 bits, but something wonky happens between gdb and
OpenOCD if I make it that size.)

Change-Id: I562a65cb0ebe5aa0edcc54c251d0fea0e26f9cb1
 2017-12-19 10:41:48 -08:00
Tim Newsome f341db9f72 WIP xml register for 0.11. 
On HiFive1, FPRs show up with no name, and misa is 0x1105 instead of
0x40001105.

Change-Id: I4ee223c905ad7d860147014e7b6394668658c6ea
 2017-12-19 10:41:48 -08:00
Tim Newsome 8926e66d3a Hide unknown registers, which probably don't exist 
Change-Id: Iffa8fa5ff4b0a01abd30fa302b7087e2011337bf
 2017-12-19 10:41:48 -08:00
Tim Newsome 26a54452d2 Fix register names. 
Use the ABI ones for every register that we have one for.

Change-Id: I2a993abff416d2652dbe026b3fb498e144a5006f
 2017-12-19 10:41:48 -08:00
Tim Newsome 7c989698a1 WIP better CSR names, and include only existing 
Change-Id: I1a234ee07c417ba56da10a61fc2bdbdcc60490a8
 2017-12-19 10:41:48 -08:00
Tim Newsome a5cb0b2270 WIP. Hide FPRs if the hart doesn't support F/D. 
Change-Id: I988c0c36f2de8157d76874a697b3c054773b787d
 2017-12-19 10:41:48 -08:00
Tim Newsome e648856a41 `make all` debug tests now pass. 
Also properly support (I think) D extension on RV32.

Change-Id: I2f0162d36e4c18c251f99b6943403cef30d17d29
 2017-12-19 10:41:48 -08:00
Tim Newsome c421fefdcb Checkpoint that seems to work. 
Change-Id: I9599aacc256f6340795097732b6f8e8869c2099f
 2017-12-19 10:41:48 -08:00
Tim Newsome 1e43d32e01 Use %ll instead of %L instead of scanf. 
Mac build barfs on L, and the manpage says they're equivalent.

Hopefully fixes #147

Change-Id: I3aa57775731f3f5ceb03097cae2a9dc6fd426dcd
 2017-12-15 15:31:36 -08:00
Tim Newsome 6aff46adcc Fix cut and paste bug. 
Now reading 64-bit FPRs on 32-bit harts using scratch memory might work.

Change-Id: Ie8c0fc689386c6e724ecab5e8c855e725fa8dd97
 2017-12-14 13:51:13 -08:00
Tim Newsome 0a65a6527d Fix build. 
Change-Id: I4e3a36fac77fefa271ae9facbaa990fa330501ae
 2017-12-11 12:58:20 -08:00
Tim Newsome e50ee46a6f
Merge pull request #131 from riscv/small_progbuf 
Support program buffers that are just 2 instructions large
 2017-12-11 12:52:31 -08:00
Tim Newsome 4d5f74fbe6 Update encoding.h. 
Change-Id: Id653500aa525746e8824ff5fd2850c62c8c21c08
 2017-11-27 13:23:33 -08:00