1ab7e910fd
Make compilation command specify architecture.
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Fixes issue #180 .
Change-Id: Icf180ae87db92840930044f1aa3129466cf43fad
2018-01-19 11:41:17 -08:00
cb543e804d
Merge pull request #184 from riscv/cleanup
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Remove dead code.
2018-01-17 15:08:30 -08:00
7f368468c8
Remove dead code.
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Change-Id: Ic90598b3dd4128dabb18ac4dc1285ca721a6a441
2018-01-15 12:07:20 -08:00
6f9585068f
Merge pull request #172 from riscv/dbus_read_comment
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Add a comment in dbus_read
2018-01-10 15:30:56 -08:00
0d60a29c21
Merge pull request #178 from riscv/cleanup
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Rename dummy variable to be correct.
2018-01-10 15:16:40 -08:00
160b794274
Merge pull request #181 from riscv/propagate_errors
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Propagate register read errors
2018-01-10 15:16:19 -08:00
29c7a76708
Muck with mstatus to always be able to read FPRs
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Change-Id: I7ff8bde4578c9ddd175c5cca370295c790cfbba7
2018-01-09 12:06:11 -08:00
fd506fa839
Propagate register read errors.
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Change-Id: Idda111377873a2236b5b91e4ffdabd2be384b47a
2018-01-08 11:53:02 -08:00
0e3869cbf6
Merge pull request #179 from riscv/multicore_hart_selection
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Select current hart before reading memory.
2018-01-05 14:07:38 -08:00
11e51af3b1
Merge pull request #173 from riscv/warn_names
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Use register names instead of numbers in warnings
2018-01-05 13:07:08 -08:00
37434ffd77
Rename dummy variable to be correct.
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Change-Id: I329404894227bb3cf563382e1adf0edda702543b
2018-01-05 13:05:33 -08:00
a6b503217d
Merge pull request #174 from riscv/delay_info
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Make delay update messages debug instead of info.
2018-01-05 13:03:14 -08:00
6f3913cedc
Select current hart before reading memory.
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This avoids trying to read memory from the wrong hart, if the current
hart was changed by an earlier call (eg. to poll()).
Change-Id: I73da1e01c8d01d68f01ac7fdd6c548380a70cfd3
2018-01-04 17:12:01 -08:00
097d62d159
Make delay update messages debug instead of info.
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They confuse users otherwise.
Change-Id: I3bc491352f5384e36c54696a0ecbf11ac623dd83
2018-01-04 13:36:53 -08:00
33aad3524b
Add a comment in dbus_read
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This just comments the current behavior
2018-01-04 13:27:35 -08:00
07e19e17cb
Use register names instead of numbers in warnings
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Change-Id: Ie2295d30fd9dfeb7590f5e34d572497a93a3ce7b
2018-01-04 13:27:18 -08:00
82529e71e0
Merge pull request #170 from riscv/strtoull
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Parse 64-bit CRC addrs even on 32-bit hosts
2018-01-03 12:48:36 -08:00
2eddd8e092
Parse 64-bit CRC addrs even on 32-bit hosts
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Change-Id: I38720163eff292b2c24f25da4e25feb8245ff672
2018-01-02 12:58:46 -08:00
f822956994
Merge pull request #169 from riscv/unused_boards
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Remove board files that I shouldn't have added
2018-01-02 12:19:55 -08:00
1ddbe70443
Remove board files that I shouldn't have added
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There are 3 other ones for the SiFive target.
Change-Id: I987331a82186a3738096cc390c91889118bf9ac2
2017-12-29 13:11:27 -08:00
ab5a98663e
Merge pull request #168 from gnu-mcu-eclipse/sifive-cfg
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Add config files for the SiFive boards
2017-12-29 11:39:57 -08:00
bd566a98bc
add configs for the SiFive boards
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- the HiFive1 board definition includes the FTDI interface
- the Arty boards require external interface definitions
2017-12-29 17:36:54 +02:00
603ed9c419
Merge pull request #167 from riscv/sifive_cfg
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Add config files for SiFive RISC-V hardware.
2017-12-28 16:34:57 -08:00
c27a777eb8
Merge pull request #165 from riscv/typo
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Fix typo.
2017-12-28 16:13:11 -08:00
8150358cde
Add config files for SiFive RISC-V hardware.
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Copied from https://github.com/gnu-mcu-eclipse/openocd
Change-Id: Ia0b3e192ca8b3bae6035623d605c9980e9bccd2c
2017-12-28 16:10:41 -08:00
52368d6ea1
Fix typo.
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Issue #164
Change-Id: I083ba0d7df72a83a802297baa25753f8d274519a
2017-12-28 11:52:59 -08:00
0774011e21
Merge pull request #163 from riscv/no_abort
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Get rid of abort() calls.
2017-12-27 14:01:46 -08:00
365c79c3ff
Get rid of abort() calls.
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Also changed a few asserts that could trigger due to broken hardware.
Fixes Issue #142 .
Change-Id: Ia2b99baa82f30ebcb2fd7e4902f0e67046ce4ed2
2017-12-27 13:45:50 -08:00
d7ed191457
Merge pull request #162 from riscv/no_abort
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Propagate error instead of calling abort().
2017-12-27 10:00:59 -08:00
06445f5743
Propagate error instead of calling abort().
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As part of this I improved the memory read/write fatal error handling a
bit. Now at least we try to leave autoexec turned off, and will even
restore the temp registers if the situation isn't too hosed for that.
Partly addresses Issue #142
Change-Id: I79fe3f862f11c6d20441f39162423357e73a40c1
2017-12-26 15:04:02 -08:00
ca700dcef0
Merge pull request #161 from riscv/dead_code
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Remove unused code.
2017-12-26 14:54:00 -08:00
4fa3d819d2
Remove unused code.
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Change-Id: Ibc72945ac76513c84d62616c0210e6013b21f7ef
2017-12-26 14:27:44 -08:00
561b0c94c0
Merge pull request #160 from riscv/style
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Conform to OpenOCD style guide.
2017-12-26 14:01:54 -08:00
d942bce996
Conform to OpenOCD style guide.
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Change-Id: I2b23ac79639ed40e9d59db5c52ea2196df0349bc
2017-12-26 11:38:11 -08:00
19d9e3e32a
Merge pull request #159 from riscv/update
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Merge changes from master
2017-12-26 11:37:41 -08:00
d2c92be73f
Merge branch 'master' into update
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Change-Id: Icec244b174cc0c67ab58961649a369db7f344824
2017-12-22 13:03:58 -08:00
6c719f0ab8
Merge pull request #156 from riscv/fespi
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fix fespi flash after registers were renamed.
2017-12-22 12:00:11 -08:00
1f66c7827b
Fix flash/run algorithm with new register names
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Change-Id: I8f539c880ee5da864956f56943411b228d8a5812
2017-12-21 16:41:50 -08:00
fadf2c1b48
Make functions static. Free memory.
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Change-Id: Iadf7b2a926d6d5abc4c8daa2f5620886bcb09b31
2017-12-21 16:23:46 -08:00
33ef457c6a
Merge pull request #155 from riscv/debug_defines
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Update debug_defines to the one used with spike.
2017-12-21 15:17:43 -08:00
a81ad34af3
Merge pull request #148 from riscv/macbuild
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Use %ll instead of %L in scanf.
2017-12-21 15:16:57 -08:00
5892b26259
Update debug_defines to the one used with spike.
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Change-Id: I627c6ee557d98239227324c33f9b89f6280cbf93
2017-12-21 15:05:12 -08:00
b01075eaa5
Merge pull request #145 from riscv/rbb_win
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Fix Windows build
2017-12-21 14:04:33 -08:00
105536089b
Merge pull request #151 from riscv/use_paren
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Use parens after if.
2017-12-21 12:50:56 -08:00
fa385bdcd5
Use parens after if.
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I'm surprised this built with gcc before.
Fixes Issue #150 .
Change-Id: I24d2957783c66ad53d5b532a4e930349a2059a97
2017-12-21 12:43:22 -08:00
1c2e3d41de
config for ESPRESSObin from Globalscale Tech. Inc.
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Change-Id: I77f536a9d2e901ebcef0a7dd0f205e5332b1d382
Signed-off-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-on: http://openocd.zylin.com/4303
Tested-by: jenkins
Reviewed-by: Forest Crossman <cyrozap@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2017-12-20 19:47:11 +00:00
84d68579eb
configs for Marvell Armada 3700
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Change-Id: I367f39c9bc9e58380d6d5b500d5368d5173d96bd
Signed-off-by: Jiri Kastner <cz172638@gmail.com>
Signed-off-by: Forest Crossman <cyrozap@gmail.com>
Reviewed-on: http://openocd.zylin.com/4302
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-12-20 19:46:20 +00:00
f13093fff7
Merge pull request #149 from riscv/xml_registers
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Send gdb an XML target description that contains only a list of registers we think exist on this target
2017-12-19 11:13:19 -08:00
11c261cd50
Add `riscv expose_csrs` command.
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This lets users tell OpenOCD which non-standard CSRs exist on their
target, that will also be accessible and whose existence will be
communicated to gdb.
Change-Id: I56163a9fcb84ad7ebe815ae74fbd9fcc208f5a9d
2017-12-19 10:41:48 -08:00
5f86f7208d
Hide supervisor registers if there is no S mode.
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Also update encoding.h.
Change-Id: I275be7de0aa1af64d13ea191b9f4ff391cfb16dc
2017-12-19 10:41:48 -08:00
Tim Newsome
Megan Wachs
Liviu Ionescu
Jiri Kastner